Sr. Clock Distribution Engineer, AI Hardware

What To Expect

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance.

What You'll Do

• Design and implement H-tree clock distribution networks — plan topology, trunk routing, and branch balancing to minimize skew across the full clock domain
• Own clock planning at the floorplan stage in Innovus — place clock roots, define clock trunk paths, and establish pre-CTS constraints that guide downstream implementation
• Drive skew optimization from floorplan through CTS closure — iterate on H-tree structure, buffer placement, and load balancing to meet skew targets
• Size clock drivers and buffers — analyze drive strength requirements and validate EMIR compliance for large clock drivers under peak switching current conditions
• Evaluate EM and IR impact of high-fanout clock networks — ensure clock trunk and driver sizing meets electromigration current density limits and IR drop budgets
• Develop CTS constraints and guidelines — define skew groups, clock latency targets, and insertion delay budgets for the CTS engine
• Validate clock distribution against post-route parasitics — analyze skew degradation and drive ECO fixes to recover timing
• Implement clock shielding strategies to protect clock trunks from aggressor coupling and noise
• Analyze and optimize clock power — balance transition times, driver strengths, and switching activity for power efficiency
• Leverage agentic AI flows to automate H-tree generation, skew analysis, and EMIR validation across clock domains

What You'll Bring

• Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience
• 7+ years of clock distribution implementation experience on high-performance SoCs
• Deep expertise in H-tree clock topology design and skew optimization
• Hands-on proficiency with Innovus for floorplan-stage clock planning and CTS implementation
• Strong understanding of EMIR concepts as applied to large clock drivers and high-fanout clock networks
• Experience sizing clock drivers for EM compliance under peak switching conditions
• Solid grasp of pre-CTS planning, CTS constraints, and post-route skew validation
• Ability to use agentic AI flows to automate clock distribution analysis and optimization

Benefits

• Competitive pay
• Medical plans
• Dental (including orthodontic coverage)
• Vision plans
• HSA Contribution
• Flexible Spending Accounts (FSA)
• Employee Stock Purchase Plans
• Other financial benefits
• Basic Life, AD&D Short-term and long-term disability insurance
• Employee Assistance Program
• Sick and Vacation time
• Paid Holidays
• Commuter benefits
• Employee discounts and perks program

Expected Compensation

$128,000 - $312,000/annual salary + cash and stock awards + benefits