Chip Simulation Engineer
Touring Capital · San Francisco Bay Area · Yesterday
Engineering$15/hrFull-time
About the role
The simulator is the core component of our AI infrastructure, running on ordinary CPUs to reproduce the behavior of AI accelerators. It serves as the foundation for our bringup agent, enabling the development of compilers, kernels, and libraries that can operate on the simulated hardware before it is physically available.
Responsibilities
- Own the models and ensure the rest of the stack builds and validates against them.
- Build performance and timing models to predict throughput and quantify gaps to peak performance.
- Develop continuous fidelity checking mechanisms to reconcile the simulator with real hardware.
- Create functional and ISA-level models from specifications or behavioral models derived from chips with incomplete specs.
- Implement RTL co-simulation to validate designs before physical silicon exists.
- Ensure the simulator's correctness as the golden reference for the entire test ladder.
- Optimize for speed and scale, making the simulator accessible and efficient for large-scale simulations.
- Integrate the simulator with the agent loop to provide seamless interaction with real hardware.
Requirements
Strong candidates should have:
- A working understanding of computer architectures and their performance characteristics.
- Experience building or extending simulators or emulators, preferably in functional or cycle-accurate modes.
- Comfort with incomplete or incorrect specifications, and the ability to reverse-engineer real behavior.
- Proficiency in Python and a systems language such as C, C++, or Rust.
- A test-first mindset, ensuring the simulator is held to a high standard.
Qualifications
Preferred qualifications include:
- Built an ISA simulator or emulator from end to end.
- Have a hardware-design background, including experience with HLS, Verilog, or time spent on the vendor side of a chip.
- Familiarity with non-GPU execution models, particularly those like warp-based GPUs, scalar tile meshes, dataflow arrays, flat SIMD, and analog MAC.
- Experience with performance modeling or roofline analysis.
- Experience building with coding agents and a good sense of when the model is trustworthy and when tests need to catch it.