Applied Research Engineer, Chip Design

About the role

NVIDIA is seeking a world-class engineer to drive applied research at the intersection of AI and ASIC design. This role puts you at the forefront of transforming chip design with the latest AI technologies.

Responsibilities

• Apply large language models, coding agents, and agentic systems to core ASIC design problems such as RTL generation, design and formal verification, PPA prediction and optimization.
• Deliver against NVIDIA’s internal chip design schedules and activities, measuring success by how much faster the ASIC teams move, not just by research output alone.
• Build robust data generation (including synthetic data) and meticulous evaluation methodology to separate working systems from demos and use evaluation to decide what to automate next.
• Wire coding agents and agentic AI into EDA and validation flows, simulating, regression testing, waveform and log analysis, and generating scripts so engineers can drive complex tasks and reduce ramp time.
• Push the limits of what’s possible in chip design with models and research harnesses on top of open-source foundations and iterate quickly from prototype to production.
• Partner closely with NVIDIA’s internal Nemotron team to improve models with domain-specific data, feedback, and post-training, feeding ASIC-design expertise back into the models.

Requirements

• MS or PhD or equivalent experience in Computer Science, Electrical/Computer Engineering, or related field.
• 8+ years of proven industry experience with domain and technical expertise in front-end ASIC (design, verification, timing).
• Project experience applying agentic AI to chip design and optimization problems, with a track record of driving ideas from conception through experimentation to production.
• Hands-on experience building LLM-based agents or AI tooling that real users depend on, including context engineering, tool integration, orchestration, and failure analysis, with a focus on evaluation.
• Experience with custom model training, fine-tuning, or post-training (SFT, RLHF/DPO) over proprietary technical data.
• Excellent self-motivation, creativity, and a passion for applied research, along with tight-knit collaboration skills and the ability to work effectively within a team.
• Experience building and maintaining infrastructure (Docker, Slurm, CI/CD, etc.).
• Excellent written and verbal communication skills, with proven experience presenting and explaining complex technical work.

Qualifications

• MS or PhD or equivalent experience in Computer Science, Electrical/Computer Engineering, or related field.
• 8+ years of proven industry experience with domain and technical expertise in front-end ASIC (design, verification, timing).
• Project experience applying agentic AI to chip design and optimization problems, with a track record of driving ideas from conception through experimentation to production.
• Hands-on experience building LLM-based agents or AI tooling that real users depend on, including context engineering, tool integration, orchestration, and failure analysis, with a focus on evaluation.
• Experience with custom model training, fine-tuning, or post-training (SFT, RLHF/DPO) over proprietary technical data.
• Excellent self-motivation, creativity, and a passion for applied research, along with tight-knit collaboration skills and the ability to work effectively within a team.
• Experience building and maintaining infrastructure (Docker, Slurm, CI/CD, etc.).
• Excellent written and verbal communication skills, with proven experience presenting and explaining complex technical work.

Skills

• Strong background in Computer Science, Electrical/Computer Engineering, or related field.
• Proven experience in ASIC design, verification, and timing.
• Experience with large language models, coding agents, and agentic systems.
• Hands-on experience with LLMs, RL, RLHF/RLAIF, post-training, evaluation, graders, synthetic data, model training, coding agents, tool-using agents, and production ML systems.
• Experience with custom model training, fine-tuning, or post-training (SFT, RLHF/DPO) over proprietary technical data.
• Excellent self-motivation, creativity, and collaboration skills.
• Experience building and maintaining infrastructure (Docker, Slurm, CI/CD, etc.).
• Strong communication skills, including the ability to present and explain complex technical work.

Benefits

• Base salary range: $192,000 - $304,750 for Level 4, and $224,000 - $356,500 for Level 5.
• Eligibility for equity and benefits.

Pay

• Base salary range: $192,000 - $304,750 for Level 4, and $224,000 - $356,500 for Level 5.

Schedule

• Full-time position.