Chip Design and Verification Methodology Engineer

Why Join Us

• Build and improve AI that is redefining how next-generation chips are designed and verified while leveraging self-verifying-and-fixing loop using AI and formal methods.
• Founded by a Stanford University professor (Prof. Subhasish Mitra) and former Samsung EVP Suk Hwan Lim and a world-class team from Google, Meta, Apple, Broadcom, Stanford, Synopsys, well-funded with eight-figure backing raised from top-tier VCs.
• Work at the intersection of AI, formal verification, and chip design, one of the most technically challenging but rewarding problems in engineering.
• Join an early team with the opportunity to shape both the product and the future of AI-native chip design.

Role Responsibilities

• Drive Verification Methodology and Environment: Take responsibility for the full verification lifecycle of AI-generated design with maximal automation. You will build the verification loop that catches bugs, generates actionable feedback, and enables AI models to improve.
• Architect Test Environments: Write clean, modular, and reusable verification environments/harnesses that can scale across customer designs. Your environments will integrate simulation, formal verification, and emulation into a unified flow.
• Build Convergence Monitoring: Develop systems that track verification progress, measure coverage, and provide guarantees about design correctness. You will define what 'done' means for AI-generated designs.
• Deep-Dive Debugging: Go beyond pass/fail logs. You will build advanced tools to read, parse, and analyze waveforms, tracing signal dependencies to pinpoint the root cause of logic failure.
• Collaborate on AI Integration: Work closely with AI engineers to ensure verification feedback improves model accuracy. Your understanding of what makes RTL correct will shape how our AI learns.
• Formal Proof Generation: Develop formal proofs for critical design paths, ensuring that safety-critical properties hold under all conditions.

Qualifications Required

• Verilog and SystemVerilog Fluency: Expert-level proficiency in writing Verilog and SystemVerilog. Understand the nuances of the language for both design (RTL) and verification (TB).
• SystemVerilog Assertions: Strong experience writing SystemVerilog Assertions. Know how to write concurrent assertions to validate complex temporal protocols.
• UVM Expertise: Deep experience with UVM methodology, including constrained-random verification, functional coverage, and scoreboards.
• Computer Architecture Fundamentals: Solid understanding of Computer Architecture and Digital Design fundamentals (e.g., pipelines, FSMs, clock domain crossing, memory hierarchy, and coherence protocols).
• Waveform Analysis: Proven ability to read and analyze simulation waveforms (using tools like Verdi, SimVision, or DVE) to resolve complex logic issues.
• Automation Mindset: Strong Python/scripting skills and a passion for automating everything that can be automated.

Preferred

• Hands-on experience with commercial formal tools such as JasperGold or VC Formal. Experience with formal apps (Connectivity, CDC, RDC, CSR) is highly desirable.
• Deep knowledge of standard on-chip interface protocols like AXI, AHB, APB, CHI, PCIe, or CXL.
• Experience at EDA vendors (Synopsys, Cadence, Siemens) or leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm).
• Familiarity with AI/ML concepts and interest in how AI can transform chip design.
• MS or PhD in Electrical Engineering or Computer Science.

Pay

$150K/yr - $300K/yr