Associate Design Verification Engineer

About The Role

As an Associate Design Verification Engineer at Analog Devices, you will contribute to the verification of digital, analog, and mixed-signal integrated circuits prior to tape-out. Working under the guidance of experienced engineers, you will develop test benches, execute verification plans, analyze simulation results, and support coverage-driven verification activities. This role offers the opportunity to build expertise in modern verification methodologies, industry-standard tools, and semiconductor product development while collaborating with cross-functional engineering teams to deliver high-quality solutions.

Key Responsibilities

• Develop and execute test benches for digital and mixed-signal design verification using SystemVerilog and established verification methodologies.
• Create and maintain verification environments that support functional and coverage-driven verification.
• Develop directed and constrained-random test cases to validate design functionality and performance.
• Perform code and functional coverage analysis to assess verification completeness and design quality.
• Debug simulation failures, analyze verification results, and identify potential design issues.
• Collaborate with design engineers to understand design requirements and verify implementation accuracy.
• Support verification planning, documentation, and design review activities.
• Utilize scripting and automation techniques to improve verification efficiency and productivity.
• Contribute to mixed-signal verification activities, including simulation and behavioral modeling where applicable.

Must-Have Skills

• SystemVerilog and Digital Verification: Knowledge of SystemVerilog and digital verification concepts, including test bench development and simulation-based verification.
• Verilog RTL Fundamentals: Understanding of RTL design principles and the ability to analyze and verify digital hardware designs.
• Verification Methodologies: Familiarity with coverage-driven verification concepts and structured verification practices.
• Scripting and Automation: Experience or coursework using scripting languages such as Python, Perl, or Tcl for automation and productivity improvements.
• Digital Interfaces and Protocols: Understanding of standard communication protocols such as I2C, SPI, UART, or similar interfaces.
• Problem Solving and Debugging: Ability to analyze simulation results, investigate failures, and resolve technical issues in a structured manner.
• Communication and Collaboration: Strong written and verbal communication skills with the ability to work effectively in a team environment.

Preferred Education And Experience

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.
• 0-2 years of experience in digital design verification or a related engineering discipline.
• New graduates with relevant academic projects, internships, or coursework in digital design, verification, or semiconductor engineering are encouraged to apply.
• Exposure to Universal Verification Methodology (UVM), constrained-random verification, or SystemVerilog Assertions (SVA) is a plus.
• Familiarity with EDA simulation and debugging tools is preferred.
• Exposure to mixed-signal simulation, analog behavioral modeling, or object-oriented programming concepts is beneficial.