ASIC Verification Engineer

About the Role

We are seeking a Senior Verification Engineer to drive the complex RTL design verification activity for a well-funded start-up developing next-generation high-speed communication technology.

Responsibilities

• Own block/cluster verification end-to-end from scratch.
• Lead testbench architecture, verification plan (Vplan) definition, and functional coverage efforts.
• Collaborate closely with design, architecture, algorithm teams, and other stakeholders.
• Support and mentor less experienced team members.
• Plan and perform verification of digital design blocks according to specifications, working with design engineers.
• Build verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for corner cases.
• Debug functionality with design engineers.
• Perform coverage collection and track metrics to ensure full functionality closure.

Requirements

• 5+ years of experience in verification (required).
• Completed at least 2 full block/system verification cycles.
• In-depth knowledge of VLSI verification flow, languages, and concepts.
• Experience with data path or data protocols, specifically Ethernet (preferred).
• Proficiency in verification methodologies (eRM, UVM).