ASIC Verification Engineer
This role is onsite with an expectation that you will primarily work from an HPE office in Sunnyvale, CA. You’ll be in the office 2 days per week.
About Us
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting-edge networking chips used to build our world-class routers and switches. Year after year, our group builds the most powerful and highest-density networking chips. As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist.
Responsibilities
- Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
- Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
- Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
- Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
- Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.
Requirements
- 5+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
- Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
- Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
- Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
- Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
Preferred Qualifications
- Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
- Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
- Exposure to emulation environments, hardware acceleration, or traffic-model integration.
- Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
- Understanding of low-power (UPF) or formal verification methodologies.
- Experience with post-silicon bring-up and debug.
- Familiarity with emulation environments and debug flows.
Benefits
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial, and emotional wellbeing.
We invest in your career with programs catered to helping you reach any career goals—whether you want to become a knowledge expert in your field or apply your skills to another division.
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We offer flexibility to manage work and personal needs.
Pay
The expected salary range for this position in California is USD 120,000 - 243,000 annually. The listed salary range reflects base salary. Variable incentives may also be offered.
Information about employee benefits offered in the US can be found at myhperewards.com.