ASIC Verification Engineer
Broadcom · Irvine, CA · 3 days ago
Quality AssuranceFull-time
Job Responsibilities
- Develop thorough understanding of IEEE Ethernet protocols.
- Understand chip architecture, microarchitecture and design specification.
- Develop advanced verification environment and testbench components in SystemVerilog UVM.
- Participate in block level and chip level verification tasks.
- Infrastructure work including developing scripts and tools for efficiency and quality improvements.
Job Requirements
- Bachelors in Engineering and 5+ years of related experience or Masters degree in Engineering and 3+ years of related experience or PhD and no experience.
- Design/Verification experience, or equivalent experience.
- Logic design, Electronic circuit design and related course work to provide a broad background in the area of ASIC design and verification.
- Proficiency with HDL language such as Verilog, SystemVerilog or VHDL is a must.
- Proficiency with C/C++ programming language and hands-on exposure to Object Oriented Programming is a big plus.
- Proficiency with scripting in various languages such as Python, PERL, TCL is a big plus.
- Self-motivated, good communicator, quick learner and good team player.
- Display positive attitude and demonstrate flexibility in day-to-day work.
Pay
The annual base salary range for this position is USD 101,000.00 To USD 162,000.00
Schedule
N/A
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time
- Competitive and comprehensive benefits package