ASIC Validation Engineer

Job Summary

We are hiring a Post-Silicon ASIC Validation Engineer to lead bring-up, validation, and characterization of complex multi-die systems integrating high-speed interconnects such as UCIe, SerDes, PCIe, and Ethernet PHYs. This role offers opportunities to work on next-generation networking SoCs and disaggregated chiplet platforms.

Responsibilities

• Drive post-silicon validation and bring-up of networking ASICs and chiplet-based SoCs.
• Own validation planning, coverage definition, and test execution across UCIe, SerDes, and networking subsystems.
• Develop automation and test infrastructure for high-speed link and protocol validation (Python).
• Perform silicon bring-up, including power sequencing, link training, and PHY initialization.
• Execute link-level and system-level validation of UCIe interfaces, die-to-die interconnects, and high-bandwidth chiplet fabrics.
• Debug complex cross-domain issues spanning RTL, firmware, analog PHY, and package-level interactions.
• Characterize signal integrity, latency, throughput, and thermal/power behavior across PVT corners.
• Collaborate with board design and test engineering teams on validation platforms, sockets, and characterization boards.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• Experience in post-silicon validation and bring-up of complex ASICs or SoCs.
• Hands-on experience with UCIe, PCIe and high-speed interconnect standards.
• Proficiency in Python for scripting, automation, and data analysis.
• Strong lab experience using oscilloscopes, BERTs, logic analyzers, and JTAG-based debuggers.
• Excellent communication skills and experience working in cross-functional silicon development teams.
• Experience with chiplet-based systems, UCIe protocol stack validation, and multi-die integration challenges (power delivery, timing, thermal).
• Familiarity with emulation or FPGA prototyping platforms for pre-silicon validation.
• Exposure to hardware/software co-validation for networking protocols or control-plane software.
• Strong knowledge of package-level interactions and signal integrity analysis for high-speed interfaces.

Qualifications

• Hands-on experience with networking ASICs and chiplet-based architectures.
• Experience with UCIe, PCIe, and high-speed interconnect standards.
• Proficiency in Python for scripting, automation, and data analysis.
• Strong lab experience with oscilloscopes, BERTs, logic analyzers, and JTAG-based debuggers.
• Experience with chiplet-based systems, UCIe protocol stack validation, and multi-die integration challenges.
• Familiarity with emulation or FPGA prototyping platforms for pre-silicon validation.
• Exposure to hardware/software co-validation for networking protocols or control-plane software.
• Strong knowledge of package-level interactions and signal integrity analysis for high-speed interfaces.

Benefits

• Opportunity to shape the future of AI infrastructure.
• Collaboration with a world-class team on groundbreaking technology.
• Direct impact on the next generation of AI infrastructure solutions.
• Transforming the performance of AI data centers.

Pay Range

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. The pay range for this role is: 185,000 - 250,000 USD per year (San Francisco Bay Area).

Location

Saratoga, CA