ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. We are leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize its utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious ASIC/SOC DFT Engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures globally. These chips enable connectivity in places where it has previously not been available, affordable, or reliable. Your efforts will help deliver solutions that expand the performance and capabilities of the Starlink network.

Responsibilities

• Evaluate design readiness for scan insertion through RTL and physical design
• Use Scan Design Rule Check (DRC) tools
• Integrate and verify Design for Test (DFT) fabrics and IP within subsystems
• Run and evaluate scan insertion through synthesis tools and refine scan insertion recipe for maximum coverage
• Run ATPG (Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meet basic coverage goals
• Run and debug non-timing and SDF annotated gate-level simulations
• Create ATPG content for use in post-silicon testing and validate that content through gate-level simulation
• Collaborate with circuit physical design, ATPG, and manufacturing teams to facilitate high-quality scan coverage in silicon

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 1+ years of professional experience working with ASICs
• Experience in scan insertion or DFT setup
• Must be willing to work extended hours and weekends as needed
• To conform to U.S. Government export regulations, applicant must be a U.S. citizen or national, U.S. lawful permanent resident (green card holder), Refugee under 8 U.S.C. §1157, or Asylee under 8 U.S.C. §1158, or be eligible to obtain required authorizations from the U.S. Department of State

Skills

• Understanding of ASIC design flow, methodologies, physical design, and verification
• Experience with high-reliability design and implementations
• Good scripting skills (csh/bash, Perl, Python, etc.)
• Familiarity with implementation or integration of design blocks using Verilog/SystemVerilog
• Familiarity with UPF (Unified Power Format), formal verification, and DRC rule checking
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player with a can-do attitude and ability to work well in a group while contributing individually
• Enjoys being challenged and learning new skills