Jobs · Engineering · Texas

ASIC DFT Engineer

Cisco · Austin, TX · 3 wk ago
Engineering$168k–$245k/yrFull-time
We need to output HTML fragment with sections: About the role? Actually we have sections: "Meet The Team" maybe as About the role? The instructions: use

for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule). We need to include sections only when posting has real specific content. We need to extract content: The posting includes: - Application window close date: "The application window is expected to close on: 11/05/2026" – this is metadata, we can fold into a short

or drop it. Probably include as a short paragraph. - "Meet The Team" paragraph describing CHG. - "Your Impact" paragraph describing role. - "Key Responsibilities" list (multiple responsibilities). Should be

  • . - "Minimum Qualifications" list (multiple bullet points). Should be
    • . - "Preferred Qualifications" list (multiple bullet points). Should be
      • . - "Why Cisco?" paragraph. - "Message to applicants applying to work in the U.S. and/or Canada:" includes salary range and benefits details. This includes Pay and Benefits sections. We need to include Pay and Benefits sections only if posting actually states them. It does state salary range and benefits. So we need a Pay section with the salary range details. Also Benefits section with benefits description. We also have schedule? Not mentioned. So no Schedule section. We need to avoid repeating job title as heading. No Job ID. We need to remove boilerplate: cookie/navigation/legal/EEO/equal-opportunity/scam-warning boilerplate, duplicated lines, application instructions. There's no explicit EEO but there is "Message to applicants applying to work in the U.S. and/or Canada:" which is not boilerplate; it's compensation info. Keep. We need to preserve all substantive information. We need to output only HTML fragment, no /, no markdown fences. We need to decide headings: Use

        for each section. Potential sections: - About the Team? Could be "Meet The Team" as About the role? The instruction says use headings like About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule. We can map "Meet The Team" to About the role. Or we could create a section "About the Team" but they said use those examples; but we can still use other headings? It says use

        for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule). It implies we should use those headings when appropriate. So we can use About the role for the team description. Responsibilities for Key Responsibilities. Requirements for Minimum Qualifications? Or Qualifications for Minimum Qualifications? They have both Requirements and Qualifications as possible headings. We could put Minimum Qualifications under Requirements, and Preferred Qualifications under Qualifications. Or we could combine. They said prefer a few substantive sections over many thin ones. So maybe we combine Minimum and Preferred into Qualifications? But they are distinct. Could do Requirements (minimum) and Qualifications (preferred). That seems reasonable. Skills? Not explicitly listed; we could omit. Benefits and Pay sections. Thus sections:

        About the role

        (Meet The Team + Your Impact? Actually Your Impact is role description; maybe combine both under About the role.) But we could also have separate sections: About the role (team description) and Your Impact (role impact). However they said prefer few sections. Could combine. Let's structure:

        Application window is expected to close on: 11/05/2026

        About the role

        [Meet The Team paragraph] [Your Impact paragraph]

        Responsibilities

        • ...
        • ...

        Requirements

        • ...
        • ...
        (minimum qualifications)

        Qualifications

        • ...
        • ...
        (preferred qualifications)

        Benefits

        [Benefits description from Message to applicants...]

        Pay

        [Salary range details]

        We need to ensure we don't include filler like "commensurate with experience". Not present. Now extract exact text. Meet The Team paragraph: "The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world." Your Impact paragraph: "You will be in the Silicon One development organization as an ASIC DFT Engineer . You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities." Note there is a double space before period after Engineer. Keep as is. Key Responsibilities list: The text after "Key Responsibilities" appears as a long sentence with no clear bullet separation but each responsibility separated by periods? Let's parse: "Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship." We need to split into list items. Each sentence seems a responsibility. So we can make each sentence a
      • . Ensure we keep punctuation. Thus:
      • Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
      • Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
      • Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
      • Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
      • The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
      • Minimum Qualifications list: After "Minimum Qualifications" we have: "Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.Prior experience working in the latest innovative trends in DFT, test and silicon engineering.Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTimePrior experience working with Gate level simulation, debugging with VCS and other simulators.Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687" We need to split sentences. Note some missing spaces after periods. We'll split at periods. Thus:
      • Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
      • Prior experience working in the latest innovative trends in DFT, test and silicon engineering.
      • Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
      • Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
      • Prior experience working with Gate level simulation, debugging with VCS and other simulators.
      • Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
      • Preferred Qualifications list: After "Preferred Qualifications" we have: "Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verificationDFT CAD development - Test Architecture, Methodology and InfrastructureTest Static Timing AnalysisPost silicon validation using DFT patterns.Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design" We need to split. There's missing spaces. We'll parse: "Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification" "DFT CAD development - Test Architecture, Methodology and Infrastructure" "Test Static Timing Analysis" "Post silicon validation using DFT patterns." "Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design" Thus list items:
      • Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
      • DFT CAD development - Test Architecture, Methodology and Infrastructure
      • Test Static Timing Analysis
      • Post silicon validation using DFT patterns.
      • Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design
      • Benefits and Pay: From "Message to applicants applying to work in the U.S. and/or Canada:" paragraph. We need to extract benefits description: It says: "U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by CiscoNon-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employeesExempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the nextAdditional paid time away may be requested to deal with critical or emergency issues for family membersOptional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies. Employees On Sales Plans Earn Performance-based Incentive Pay On Top Of Their Base Salary, Which Is Split Between Quota And Non-quota Components, Subject To The Applicable Cisco Plan. For Quota-based Incentive Pay, Cisco Typically Pays As Follows .75% of incentive target for each 1% of revenue attainment up to

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