ASIC Physical Design Engineer

About the role

Responsible for all aspects of physical implementation of SOC devices, from RTL to GDSII.

Responsibilities

• Execute physical design tasks including floorplanning, placement, clock tree synthesis, routing, and design closure.
• Drive place-and-route using industry-standard EDA tools, optimizing for timing, power, area, and signal integrity.
• Perform static timing analysis and verification across multiple modes, resolving timing and constraints issues.
• Support physical signoff activities such as DRC, LVS, extraction, IR drop, electromigration, and crosstalk analysis.
• Collaborate with RTL, verification, DFT, analog, packaging, and architecture teams to ensure manufacturability and tapeout readiness.
• Develop scripts and documentation to improve design methodology, automation, and quality.

Requirements

• Bachelor’s in Electrical Engineering or related field.
• 5+ years of ASIC physical design experience.
• Hands-on experience with RTL-to-GDSII flow, floorplanning, power planning, and design closure.
• Knowledge of static timing analysis, multi-corner verification, and signoff checks.
• Proficiency with industry tools from Cadence, Synopsys, or Siemens EDA.
• Scripting skills in Tcl, Python, Perl, or Shell for flow support and debugging.

Preferred Skills

• 10+ years of experience, including leadership roles in complex ASIC or SoC projects.
• Expertise in timing closure, signoff, and managing internal/external design teams.
• Deep understanding of implementation trade-offs and methodology optimization.