ASIC Physical Design Engineer

About the role

As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. You will work as an individual contributor leading the RTL-to-GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area (PPA) targets.

Responsibilities

• Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm)
• Conduct hierarchical floor planning, place and route, and clock/power distribution
• Perform static timing analysis (STA) and drive timing closure for multi-mode/multi-corner designs
• Lead the physical design of assigned blocks, ensuring quality and alignment to project timelines
• Develop and maintain automated scripts to improve design flow efficiency and methodology
• Collaborate with RTL and DFT teams to debug and resolve complex physical implementation issues
• Implement test plans and participate in design reviews to ensure robust, high-quality work
• Contribute to the refinement of design methodologies and best practices within the engineering team
• Document functional specifications and track progress for assigned project landmarks

Requirements

• Bachelor's degree in Engineering + 5 years of related experience, or Master's degree in Engineering + 3 years of related experience
• Demonstrated experience in ASIC physical design and implementation
• Experience working with hierarchical floor planning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology
• Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes

Preferred Qualifications

• Experience with Scripting using languages such as TCL, Perl, Python, etc.
• Place & Route experience using tools such as Cadence Innovus or Synopsys ICC2
• Experience with formal equivalence check, timing closure, signal integrity, EMIR, physical verification
• Experience with Static Timing Analysis including tools such as Tempus
• Experience with block level EMIR closure
• Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre

Benefits

At Cisco, we offer competitive compensation, comprehensive benefits, and a supportive work environment. The starting salary range for this position is $128,600.00 to $184,900.00, reflecting the projected salary range for new hires in U.S. and Canadian locations. Additional benefits include medical, dental, and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Employees may also receive grants of Cisco restricted stock units, paid time off, and additional paid days off for personal wellness. For quota-based sales roles, incentive compensation is included in the base pay range.