ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)

This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants residing within the United States.

About the team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Requirements

• Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 4+ years of relevant signal and power integrity experience.
• High-Speed Design & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
• SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
• Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
• Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.

Preferred Qualifications

• Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
• Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
• Experience with die-to-die interfaces (UCIe or proprietary).
• Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
• Working knowledge of Vector Network Analysis.
• Basic knowledge of IBIS.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Pay

The starting salary range for this position is $192,400.00 to $275,800.00 for new hires in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below:

• New York City Metro Area: $214,100.00 - $356,300.00
• Non-Metro New York State & Washington State: $192,400.00 - $317,200.00

For quota-based sales roles on Cisco’s sales plan, the ranges provided include base pay and sales target incentive compensation combined.

Benefits

• Medical, dental, and vision insurance
• 401(k) plan with a Cisco matching contribution
• Paid parental leave
• Short and long-term disability coverage
• Basic life insurance
• Restricted stock units (RSUs) which vest following continued employment
• Paid time off:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
  • 1 paid day off for employee’s birthday
  • Paid year-end holiday shutdown
  • 4 paid days off for personal wellness
  • Non-exempt employees: 16 days of paid vacation time per full calendar year, accrued at 4.92 hours per pay period
  • Exempt employees: Flexible vacation time off with no defined limit (subject to availability and business limitations)
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward
  • Additional paid time away for critical or emergency family issues
  • Optional 10 paid days per full calendar year to volunteer
• Annual bonuses for non-sales roles, subject to Cisco’s policies
• For sales roles: Performance-based incentive pay split between quota and non-quota components