Signal & Power Integrity Hardware ASIC Simulation Engineer Lead (Remote)

About the team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we're able to think differently, experiment more, and work quickly.

Cisco Silicon One is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world's most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies.

Your impact

We are seeking a highly qualified Signal and Power Integrity Technical Lead to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.

• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Minimum qualifications

• Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.
• High-Speed Design & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
• SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
• Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
• Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.

Preferred qualifications

• Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
• Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
• Experience with die-to-die interfaces (UCIe or proprietary).
• Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
• Working knowledge of Vector Network Analysis.
• Basic knowledge of IBIS.

Pay

The starting salary range for this position is $183,800.00 to $263,600.00 (U.S. and Canada locations), not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training.

Benefits

• Medical, dental and vision insurance
• 401(k) plan with a Cisco matching contribution
• Paid parental leave
• Short and long-term disability coverage
• Basic life insurance
• Grants of Cisco restricted stock units (vesting following continued employment for defined periods of time)
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee's birthday
• Paid year-end holiday shutdown
• 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees: 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees: flexible vacation time off program with no defined limit (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• Annual bonuses for non-sales roles (subject to Cisco's policies)
• Performance-based incentive pay for sales roles (quota and non-quota components, with incentive rates at or above 1% for each 1% of attainment beyond 100%, no cap on incentive compensation)

Schedule

This position is located in San Jose, CA, and is open to remote applicants residing within the United States.

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