Asic Engineer

About the role

This role leads a team of engineers designing complex flip-chip BGA packages for advanced ASICs that power artificial intelligence, networking, high-performance computing, and 5G base stations. You will manage and mentor a worldwide R&D team, drive high-performance package designs featuring cutting-edge SerDes, high-bandwidth memory, and advanced power delivery, and shape technical methodologies and project management practices for multiple concurrent programs.

Responsibilities

• Lead and manage a team of IC package design engineers focused on complex flip-chip BGA packages for industry-leading ASICs.
• Oversee and contribute to the design of packages that support high-speed SerDes (448G and higher), 5G RF/microwave ADC/DAC, HBM, DDR5, and very high power delivery requirements.
• Create, maintain, and track project plans for 20+ concurrent package designs, including defining scope, schedules, and resource allocation.
• Organize team and customer activities to keep projects on schedule, ensuring alignment across engineering, customers, and vendors.
• Communicate project plans, status, next steps, and risks clearly and regularly to stakeholders across multiple time zones.
• Develop and refine technical methodologies for package design, including best practices, standards, and workflows.
• Steer package technology choices and design rules in collaboration with team members and cross-functional partners.
• Apply deep knowledge of package-level signal integrity and power integrity to guide and review package designs.
• Collaborate with a worldwide R&D team, coordinating co-design activities with internal team members and external vendor designers.
• Ensure that substrate and package designs integrate seamlessly into overall ASIC design and manufacturing flows.
• Manage and review design data, including .mcm files, package spreadsheets, and drawings such as POD, lid, and substrate documentation.
• Evaluate and balance DFx trade-offs (design for manufacturability, reliability, assurance of supply, signal integrity, power integrity, and other factors) in package designs.
• Guide and review layout activities, ensuring adherence to design rules and performance targets.
• Direct and interpret SI/PI extractions and simulations to validate and optimize package performance.
• Promote and support automation code development to improve design efficiency, quality, and repeatability.
• Oversee mechanical and thermal modeling of packages to ensure robust operation under target conditions.
• Participate in and support new business quotation activities related to package design, including effort estimation and technical input.
• Collaborate closely with customers, vendors, and cross-functional teams (such as PCB layout and ASIC design teams) to ensure cohesive solutions.
• Understand the skill sets and strengths of each team member to maximize productivity, engagement, and retention.
• Encourage strong self-management and organizational practices within the team, fostering accountability and ownership.

Requirements

• BSEE, MSEE, or a similar degree in an appropriate engineering field.
• 12+ years of experience in flip-chip BGA package design, including high-speed SerDes applications.
• Minimum of 3 years of management experience leading engineering teams and projects.
• Hands-on experience with flip-chip package design for ASICs, including complex power delivery requirements.
• Strong knowledge of high-speed SerDes design considerations within package environments (including 448G and higher).
• Proficiency in package-level signal integrity (SI) and power integrity and their application to real-world package designs.
• Experience with the complete package-design lifecycle, from concept through release to manufacturing.
• Understanding of how substrate and package designs fit into overall ASIC design and manufacturing flows.
• Ability to work effectively with worldwide teams across multiple time zones.
• Strong project management skills, including creating and tracking detailed project plans for multiple concurrent designs.
• Proven ability to communicate plans, status, next steps, and risks clearly to technical and non-technical stakeholders.
• Demonstrated self-management and organizational skills in a complex engineering environment.
• Solid understanding of ASIC chip and package co-design principles.

Qualifications

• Previous experience managing both people and technical projects in an IC packaging or related domain.
• Familiarity with design data formats and artifacts such as .mcm files, package spreadsheets, and drawings (POD, lid, substrate).
• Experience evaluating DFx (design for manufacturability, reliability, assurance of supply, SI/PI, and related factors) trade-offs in package design.
• Experience in layout processes and tools used for advanced IC package design.
• Experience performing or overseeing SI/PI extractions and simulations for high-speed and high-power packages.
• Exposure to automation code development to streamline and standardize design workflows.
• Experience with mechanical and thermal modeling of IC packages.
• Involvement in new business quotation activities related to package design and development.
• Strong customer, vendor, and cross-functional collaboration skills, particularly with PCB layout and ASIC design teams.

Skills

• BSEE, MSEE, or a similar degree in an appropriate engineering field.
• 12+ years of experience in flip-chip BGA package design, including high-speed SerDes applications.
• Minimum of 3 years of management experience leading engineering teams and projects.
• Hands-on experience with flip-chip package design for ASICs, including complex power delivery requirements.
• Strong knowledge of high-speed SerDes design considerations within package environments (including 448G and higher).
• Proficiency in package-level signal integrity (SI) and power integrity and their application to real-world package designs.
• Experience with the complete package-design lifecycle, from concept through release to manufacturing.
• Understanding of how substrate and package designs fit into overall ASIC design and manufacturing flows.
• Ability to work effectively with worldwide teams across multiple time zones.
• Strong project management skills, including creating and tracking detailed project plans for multiple concurrent designs.
• Proven ability to communicate plans, status, next steps, and risks clearly to technical and non-technical stakeholders.
• Demonstrated self-management and organizational skills in a complex engineering environment.
• Solid understanding of ASIC chip and package co-design principles.

Benefits

The pay range for this position is $140000.00 - $240000.00/yr. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Brotherhood offers a competitive and comprehensive benefits package:

• Medical, dental and vision plans.
• 401(K) participation including company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company paid holidays, paid sick leave and vacation time.

The company follows all applicable laws for Paid Family Leave and other leaves of absence.

This is a fully onsite position in Broomfield, CO.