AI Data Center High-Speed Interconnect Architect
BizLink Group · Fremont, CA · 4 wk ago
EngineeringFull-time
Key Responsibilities
- Architect and optimize high-speed interconnect solutions, including backplanes, co-packaged copper, OSFP, OSFP-X, and onboard connectors, for AI/ML and HPC platforms.
- Achieve equilibrium among performance, signal integrity, power consumption, cost efficiency, and manufacturing feasibility.
- Lead the assessment and selection of interconnect technologies (e.g., NVLINK, UALINK, PCIe, CXL), considering evolving standards and future scalability imperatives.
- Collaborate with signal and power integrity engineers to ensure robust high-speed data transmission and adherence to electrical and EMI/EMC standards.
- Engage with hardware, system, packaging, and software development teams to integrate interconnect solutions into AI server and rack architectures.
- Represent the organization in standards bodies (e.g., OCP, PCI-SIG, UALINK, IEEE, CXL Consortium), influence the formulation of next-generation interconnect standards, and monitor industry trends.
- Interact with hyperscalers, OEMs, and technology partners to ascertain requirements, address challenges, and facilitate the collaborative development of innovative solutions.
- Author technical specifications, architecture documents, and contribute to the product roadmap for high-speed interconnects.
Job Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
- Minimum of 10 years of professional experience in high-speed interconnect architecture, signal integrity, or system design for compute, networking, or AI platforms.
- Extensive expertise in high-speed protocols (NVLINK, UALINK, PCIe, CXL, Ethernet, InfiniBand, OSFP, OSFP-X) and advanced connector/cabling technologies.
- Comprehensive knowledge of signal integrity, power integrity, PCB/package/system design, and relevant simulation tools.
- Prominent experience in participating in or influencing industry standards development.
- Exceptional communication and cross-functional leadership proficiencies.
- Familiarity with hardware/software co-design and performance analysis for AI/HPC workloads is advantageous.