Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)

About the role

We are seeking an experienced Physical Design Lead to join our Silicon Technology Engineering (STE) organization within the Digital ASIC Group. This team develops advanced-node, large-scale mixed-signal ASICs that are foundational to Teradyne’s next-generation SoC and memory test platforms.

Responsibilities

• Lead and mentor a team of physical design engineers across the full project lifecycle
• Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
• Develop and own chip floorplans, timing budgets, power estimates, and pin planning
• Partner with design teams to develop high-quality SDC constraints
• Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
• Support hands-on place-and-route (P&R) for critical and high-speed blocks
• Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
• Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
• Ensure robust signoff closure including DRC/LVS and EM/IR analysis
• Develop, enhance, and maintain physical design tool flows and automation

Requirements

• 10+ years of hands-on ASIC physical design experience, including leadership of large or complex PD projects
• Proven experience at advanced technology nodes (16nm and below)
• Deep expertise in RTL-to-GDSII flows and timing closure
• Strong understanding of STA, constraints development, and signoff methodologies
• Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes)
• Proficiency with industry-standard EDA tools (Cadence preferred)
• Strong scripting and automation skills using Tcl, Python, and/or Make
• Ability to lead technically, communicate clearly, and collaborate across disciplines
• BS or MS in Electrical Engineering (or equivalent practical experience)

Qualifications

• BS or MS in Electrical Engineering (or equivalent practical experience)

Skills

• Hands-on ASIC physical design experience
• Advanced technology node experience (16nm and below)
• RTL-to-GDSII flows and timing closure expertise
• STA, constraints development, and signoff methodologies knowledge
• High-speed and complex IP integration experience
• Industry-standard EDA tools proficiency (Cadence preferred)
• Tcl, Python, and/or Make scripting and automation skills
• Technical leadership and mentoring abilities

Benefits

• Competitive compensation, benefits, and career growth opportunities
• Work on cutting-edge silicon that directly impacts the semiconductor ecosystem
• High technical ownership and visibility
• Collaborative, engineering-driven culture

Pay

The base salary range for this role is $192,300 to $307,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Schedule

N/A