Vice President of Foundry Operations

Quantum Computing Inc. (QCi) (Nasdaq: QUBT) is an innovative, integrated photonics company that provides accessible and affordable quantum machines to the world today. Our products are designed to operate at room temperature and low power at an affordable cost, offering unique capabilities in high-performance computing, artificial intelligence, cyber security, and remote sensing applications.

About the role

This position directs all development, pilot-line, and high-volume manufacturing (HVM) operations for a $100M production-scale facility utilizing sub-micron hybrid bonding technology and supporting over 100 on-site employees. The role bridges low-volume R&D scaling for multi-size, multi-substrate architectures with the operational rigor of a 24/7 high-volume 300mm manufacturing line.

Responsibilities

• P&L & Dual-Mode Operations: Own the operating budget, CapEx, and line-balancing for a hybrid facility that simultaneously handles high-mix/low-volume R&D (50mm–200mm) and high-volume 300mm production.
• Hybrid Bonding Execution: Drive operational excellence and yield optimization across sub-micron particle-sensitive processes, specifically Die-to-Wafer (D2W) and Wafer-to-Wafer (W2W) hybrid bonding.
• Multi-Substrate Engineering Control: Supervise the intake, handling, and custom processing variations for a wide variety of substrate materials (e.g., Silicon, Glass, Compound Semiconductors).
• Advanced Process Management: Oversee a complex process flow including Custom BEoL (Back-End-of-Line), TSV (Through-Silicon Via) insertion and reveal, precision wafer thinning, and silicon/glass interposer fabrication.
• Team Leadership & Scale: Lead, mentor, and align a 100+ person multi-disciplinary team comprising cleanroom operators, equipment technicians, pilot-line development engineers, and HVM production supervisors.
• Yield & Cleanroom Discipline: Enforce strict surface-preparation and contamination-control protocols required for successful hybrid bonding, ensuring high reliability and SPC compliance.

Requirements

• Education: Bachelor’s degree in Materials Science, Chemical, Mechanical, or Electrical Engineering; Master’s or Ph.D. with a focus on advanced semiconductor packaging is highly preferred.
• Experience: Minimum 10 years in advanced semiconductor manufacturing or packaging, with at least 5 years of experience managing a fab line that bridges pilot development and high-volume manufacturing.
• Technical Expertise: Direct operational exposure to hybrid bonding, TSV reveal, CMP (Chemical Mechanical Planarization) for surface flatness, precision wafer thinning/carrier bonding, and multi-size wafer handling (50mm to 300mm).
• Operational Capabilities: Demonstrated ability to manage rapid product-mix changes on development lines while maintaining uptime, OTD (On-Time Delivery), and cycle-time discipline on an HVM line.