Two Sigma Securities, Hardware Engineer

Position Summary

Two Sigma is a leading quantitative investment management and trading firm. The company applies a scientific approach to investing, combining cutting-edge technology, artificial intelligence, data science, and quantitative research with rigorous human inquiry to capitalize on market opportunities and deliver alpha for investors. Our team of engineers, quantitative researchers and data scientists looks beyond the traditional to test hypotheses and develop creative solutions to some of the world’s most complex economic problems. Two Sigma Securities brings a scientific approach to systematic trading and risk management to make markets more efficient. Our team trades over 10,000 US equities and 4,000 listed options, leveraging our high performance trading system to execute over 850 million shares per day. Two Sigma Securities is entering an exciting growth phase. We value the insights of our colleagues and encourage them to innovate and shape their own work agenda. New joiners use our proprietary platform to work on diverse projects. From building next generation trading technologies and researching novel AI and machine learning techniques to enhancing our strategies and deploying automation, our team is pushing the frontier in systematic trading.

Responsibilities

• Develop, test, and deploy cutting-edge FPGA systems for trading applications
• Contribute to the hardware team's library of optimized, reusable components
• Collaborate with traders and modelers to devise optimal hardware implementations of trading algorithms
• Partition hardware and software tasks with software engineers for the most effective system design
• Optimize network architecture and latency alongside network engineers
• Build tools to monitor, analyze, and improve system performance

Qualifications

• Minimum 1 year of experience required; 5+ years of experience preferred in RTL design and verification for ASIC or FPGAS
• Strong RTL design, optimization, and debugging skills, with proficiency in SystemVerilog and Python
• Working knowledge of FPGA or ASIC architectures, FPGA toolchains, and timing analysis
• Knowledge of network communication protocols
• Experience with C++ is a plus

Benefits

• Core Benefits: Fully paid medical and dental insurance premiums for employees and dependents, competitive 401k match, employer-paid life & disability insurance
• Perks: Onsite gyms with laundry service, wellness activities, casual dress, snacks, game rooms
• Learning: Tuition reimbursement, conference and training sponsorship
• Time Off: Generous vacation and unlimited sick days, competitive paid caregiver leaves
• Hybrid Work Policy: Flexible in-office days with budget for home office setup

Pay

The base pay for this role will be between $165,000 and $300,000. This role may also be eligible for other forms of compensation and benefits, such as a discretionary bonus, health, dental and other wellness plans and 401(k) contributions. Discretionary bonus can be a significant portion of total compensation. Actual compensation for successful candidates will be carefully determined based on a number of factors, including their skills, qualifications and experience.