Top Level Physical Design Engineer
Who You Are
A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
Passionate about optimizing chip-level implementations for power, performance, and area.
Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules.
What We Need
- 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
- Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
- Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
- Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.
What You Will Learn
- Advanced techniques for chiplet integration and next-generation packaging co-design.
- Strategies for optimizing massive designs with complex power domains and clock architectures.
- Methods for driving successful chip-level closure through effective cross-functional collaboration.
Compensation
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets.
Qualifications
- Experience, skills, education, background and location all impact the actual offer made.
Benefits
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Pay
Compensation for this role ranges from $100k - $500k including base and variable compensation targets.
Schedule
This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.