The Principal Test Engineer - Security and Provisioning

Responsibilities

• Own the end-to-end ATE provisioning strategy for secure manufacturing flows, including lifecycle state transitions, secure boot enablement, device identity, debug lock/unlock policy, and production fuse programming.
• Define and implement manufacturing-friendly fuse and provisioning flows, including fuse write, readback, verify, margin read, error handling, retry limits, binning, audit logging, and clear pass/fail criteria.
• Partner with DV teams to validate provisioning sequences, security blobs, fuse programming models, lifecycle state transitions, negative/error scenarios, and security state-machine behavior before silicon execution.
• Develop, simulate, validate, and debug Advantest 93K test methods, digital patterns, datalogging, and production flows for secure provisioning, fuse programming, lifecycle validation, and post-provisioning integrity checks.
• Define production controls and documentation to prevent over-fusing, incorrect lifecycle transition, partial provisioning, duplicate programming, wrong-blob usage, or unauthorized debug enablement, including traceability, release criteria, debug procedures, and CP/FT/SLT/HVM handoff.

Requirements

• 10+ years of experience in semiconductor manufacturing, ATE test development, product engineering, production test, or silicon bring-up for complex SoCs or advanced semiconductor devices.
• Strong hands-on experience with Advantest 93K ATE test development, including SmarTest 7 / SmarTest 8, digital patterns, STIL/pattern generation, test methods, debug flows, datalogging, binning, and production test integration.
• Experience with eFuse, OTP, non-volatile fuse programming, fuse controllers, lifecycle controllers, JTAG indirect access, readback/verify flows, margin validation, and manufacturing-safe fuse programming controls.
• Prior experience with security lifecycle transitions, secure debug states, device provisioning, key/certificate/blob handling, secure boot enablement, debug authentication, DICE, attestation, Root-of-Trust, RSE, Caliptra, or equivalent secure manufacturing flows.
• Ability to understand fuse maps, security registers, JTAG/DAP/APB/AXI access paths, manufacturing access restrictions, provisioning appliances, and security/debug infrastructure requirements.
• Experience working with DV and design teams to validate test sequences, provisioning blobs, lifecycle state machines, fuse models, negative/error scenarios, and silicon-to-ATE correlation before production release.
• Strong understanding of wafer sort, final test, SLT, HVM release, production quality controls, traceability, data integrity, manufacturing guardrails, and cross-functional debug across silicon, ATE, firmware, security, and design teams.