Technology Development Foundry Engineering - Staff Yield Engineer
About the role
At the heart of Intel's groundbreaking product advancements, the Logic Technology Development (LTD) organization drives process technology innovation to propel Intel's Foundry strategy. As a Foundry Technology Development - Staff Yield Engineer, you will be at the forefront of Intel's collaboration with foundry partners, guiding customers through product development from testing and validation to New Product Introduction (NPI) and High Volume Manufacturing (HVM). You will oversee the wafer manufacturing process, ensure seamless transitions into volume production, and shape the future of the semiconductor industry.
Responsibilities
- Serve as the yield point of contact through the cycle of foundry product development, from design to initial High Volume Manufacturing (HVM).
- Define yield goals and roadmaps for foundry customer silicon by collaborating with Intel Foundry Services (IFS), Technology Development (TD), and Product Integration.
- Collaborate with TD Process Integration, Device, Defect Metro, and Lab teams to identify yield detractors and yield enhancement opportunities for foundry customer silicon.
- Provide yield and defect density projections for different types of customer silicon, including test chips, shuttles, and products.
- Track inline process and non-process changes to incorporate changepoints into the yield prediction model.
- Develop yield models to identify potential parametric and defective loss components and support Process Integration, Device, and Module teams in eliminating systematic yield losses.
- Support yield analysis of logic, SRAM, and other device types on foundry customer silicon.
- Establish correlations between critical inline metrics and yield for better inline control and end-of-line projection.
- Engage with Product Integration and Device teams in customer silicon execution, such as skew split planning and DOE.
- Lead investigations and root-causing on yield signals for foundry customer silicon.
- Identify opportunities to optimize foundry product development operational systems and methodologies to improve efficiency and standardization.
- Act as the technical interface between the foundry and both internal stakeholders and external customers.
Requirements
Minimum qualifications required to be considered for this position:
- Bachelor's Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or other relevant engineering or physical science discipline with 6+ years of relevant work experience, OR
- Master's Degree in the same fields with 4+ years of relevant work experience, OR
- PhD in the same fields with 2+ years of industry experience.
- The years of relevant work experience must be in at least one of the following areas:
- Semiconductor yield engineering.
- Analysis of yield post-silicon yield signals and root-causing.
Skills
Preferred qualifications (considered a plus factor in identifying top candidates):
- 3+ years of semiconductor direct yield analysis and engineering experience.
- 3+ years of experience in yield pareto, projection, and yield roadmap construction.
- 3+ years of experience within a foundry team or foundry customer yield collaboration.
- 3+ years of experience interpreting product data, including inline, e-test, and SORT data, finding failure root causes, and driving solutions.
- Knowledge of inline inspection methods, electrical test structures, and SORT programs.
- Exposure to fabless design house product development.
- Foundry customer service experience with evidence of strong customer orientation.
Benefits
We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock, bonuses, and benefit programs such as health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Pay
Annual Salary Range for jobs which could be performed in the US: $148,100.00 - $209,100.00. Salary range dependent on location and experience.
Schedule
This role is eligible for our hybrid work model, which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Other locations: US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara.