Technical Program Manager – GPU Floorplanning

About the role

NVIDIA is seeking a highly capable Technical Program Manager (TPM) to partner closely with our GPU Floorplan team and multi-functional collaborators in driving the execution of large, complex, multi-die SoC and chiplet programs. This role sits at the intersection of deep technical understanding and disciplined program execution.

Responsibilities

• Own and drive end-to-end execution tracking for large-scale GPU / SoC floorplan programs across multiple dies and chiplets.
• Build and maintain integrated program views spanning breakthroughs, dependencies, risks, and cross-team interactions.
• Ensure plans from multiple chiplet/die owners roll up into a cohesive, executable project-level view.
• Partner closely with floorplan and technical leads to identify, track, and prioritize critical technical issues impacting area, wiring, timing, and schedule.
• Proactively identify execution risks, misalignment, and early warning signals across the program.
• Drive structured risk reviews and mitigation planning, ensuring issues are visible early rather than discovered late.
• Serve as a primary coordination point between floorplan and partner teams including architecture, RTL, PD, DFT, package, design, and tooling.
• Improve the quality, consistency, and predictability of interactions across teams.
• Help rationalize and mature program management processes as programs grow in size and complexity.
• Champion better tooling, dashboards, and structured ways of working that reduce overhead on technical leads.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering or equivalent experience.
• 10+ years of relevant working experience.
• Strong program or technical project management experience in complex hardware or silicon development programs.
• Proven ability to manage highly interdependent, multi-threaded execution across multiple partners.
• Sufficient technical depth to understand and engage on topics such as SoC architecture, physical design flows, floorplanning, or chip integration (not hands-on implementation, but informed judgment).
• Excellent written and verbal communication skills, with the ability to synthesize complexity into clear status and decisions.

Qualifications

• Prior experience supporting floorplan, physical design, chip integration, or early silicon planning teams.
• Experience working on multi-die, chiplet-based, or large SoC programs.
• Able to operate effectively in environments with incomplete data, evolving requirements, and tight milestones.
• Strong judgment in prioritization - knowing when to push, when to call out, and when to unblock quietly.

Skills

• Strong program or technical project management experience.
• Technical depth in SoC architecture, physical design flows, floorplanning, or chip integration.
• Effective communication and synthesis skills.
• Ability to manage interdependent projects and prioritize tasks.

Benefits

• Comprehensive benefits package.
• Unprecedented growth in engineering teams.
• Opportunity to work with highly dedicated and passionate individuals.

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $168,000 - $258,750 for Level 4, and $200,000 - $322,000 for Level 5.

Schedule

N/A