System Verification Co-Design Engineer - Speed and Rel

About the role

SCG sits at the crossroads of design, architecture, marketing, and productization—owning the journey from the architecture stage through final product definition across Gaming, Datacenter, Automotive, and Embedded markets. As a System Verification CoDesign Engineer, you will work on system-level speed features, develop the verification collaterals and automation infrastructure to characterize and validate them, and lead debug of the complex silicon issues that stand between a program and on-time shipment.

Responsibilities

• Collaborate cross-functionally with system architects, hardware, firmware/software, process/reliability, and operations teams to co-design system-level speed features and deliver industry-defining products.
• Understand system level behavior and speed reliability margins, bounding box constraints and identify solutions that optimize margins.
• Translate hardware features and architectural requirements into verification techniques that achieve full coverage across testing flows.
• Perform closed loop validation by correlating silicon behavior against timing simulation and design expectations; provide actionable feedback to improve future designs.
• Define, prototype, and refine pre- and post-silicon bring-up flows to ensure product quality, performance, and schedule efficiency.
• Design and implement automation tools for system speed modeling; apply AI and LLM-assisted workflows (e.g., automated log analysis, pattern detection, scripting acceleration) to compress characterization and debug cycles.
• Architect and influence testability features critical to performance, power, and reliability in partnership with design, DFx, and ATE teams.
• Lead debug of complex silicon and system-level issues, including show-stopper defects, to enable on-time product shipment.

Requirements

• MS in EE, CE, Systems Engineering, or equivalent experience.
• 4+ years of experience in a related hardware engineering role.
• Hands-on experience with silicon bring-up, frequency and power characterization, PPA analysis in pre- and post-silicon phases, System/Platform level understanding, tester-to-system correlation, and lab instrumentation (oscilloscopes, multimeters, DAQs).
• Scripting proficiency in Python and/or Perl; comfortable in Windows, Linux, and Android environments.
• Familiarity with statistical methods and data analysis tools (JMP or equivalent).
• Demonstrated use of AI or LLM-based tools (e.g., Claude, Copilot, ChatGPT) in an engineering workflow—scripting acceleration, log triage, data analysis—with clear judgment about output validation and where automation introduces risk.

Qualifications

• Background in gaming, automotive, or datacenter segments.
• Experience building or deploying AI-assisted characterization, log analysis, or debug automation workflows in a production silicon environment.
• Familiarity with LLM evaluation, prompt engineering, or agentic scripting pipelines applied to silicon data analysis.

Skills

• Strong technical skills in hardware engineering, particularly in system-level speed features and verification.
• Experience with AI and LLM tools in engineering workflows.
• Excellent communication and collaboration skills.
• Ability to lead and debug complex silicon issues.

Benefits

Competitive salaries and a generous benefits package, including equity.

Pay

Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.

Schedule

Applications for this job will be accepted at least until July 11, 2026.