Static Timing Analysis (STA) Engineer
About the role
Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Static Timing Analysis (STA) Engineer to join our Boeing Electronic Products team located in Tukwila, WA and at the heart of Boeing’s products - ASICs and FPGAs. Our Electronics Products team goal is to be Boeing’s sole source for electronics. We’ve grown by over 400% and continue to have new opportunities to support more Boeing Platforms.
Responsibilities
- Responsible for STA analysis and convergence throughout the ASIC cycle
- Find solution for intricate timing paths (Digital, analog and mixed signal)
- Facilitate STA methodology in collaboration with other STA leaders
- Generate timing constraints for multiple ASICs and FPGAs
- Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
- Responsible for intricate cross domain timing path closure
- Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
- Programming skills with Python, TCL, Perl, Unix shell etc.
- Help train new engineers
Requirements
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
5+ years of experience with timing closure on ASICs and FPGAs
Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out
Good understanding of RTL to GDS flow
Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
Able to work with large physical design team to make the timing convergence successful
Qualifications
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics or Chemistry or non-US equivalent qualifications directly related to the work statement
5+ years of experience with timing closure on ASICs and FPGAs
Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out
Good understanding of RTL to GDS flow
Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
Able to work with large physical design team to make the timing convergence successful