Staff SoC DFT Engineer, HBM

About the role

You will join an inclusive, innovation-driven team focused on building technologies that power virtual reality, neural networks, and next-generation computing. In this role, you will own design for test (DFT) solutions for complex high-bandwidth memory (HBM) system-on-chip (SoC) base-die designs. Your work will directly enable manufacturability, quality, and successful silicon bring-up across current and future HBM generations.

Responsibilities

• Own SoC-level design for test (DFT) architecture and implementation, including scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (Joint Test Action Group, JTAG), and test access architectures for HBM base-die designs.
• Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels while partnering closely with register-transfer level (RTL) design and SoC integration teams.
• Execute and sign off DFT flows, including linting, clock-domain crossing (CDC) checks, DFT rule checks, automatic test pattern generation (ATPG) readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and design rule check/layout versus schematic (DRC/LVS) signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, smooth pre-silicon debug, and post-silicon bring-up.
• Partner with computer-aided design (CAD) and methodology teams to standardize and improve DFT flows, contribute to cross-group technical reviews, mentor engineers as appropriate, and drive innovation for future HBM generations.

Requirements

• Strong hands-on experience with SoC design for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience working across full RTL-to-GDS SoC flows and collaborating with synthesis, static timing analysis (STA), and physical design teams.
• Proficiency using industry-standard electronic design automation (EDA) tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital application-specific integrated circuits (ASICs) or SoCs.

Preferred Qualifications

• Experience with large, complex SoCs that integrate multiple intellectual property (IP) blocks and subsystems.
• Strong RTL debugging, design analysis, and problem-solving skills.
• Experience using scripting languages such as Python, Tcl, or Perl for flow automation.
• Ability to communicate clearly and collaborate effectively across global, cross-functional teams.
• Familiarity with memory systems such as dynamic random-access memory (DRAM), high-bandwidth memory (HBM), and related JEDEC specifications.

Benefits

• A choice of medical, dental, and vision plans enabling team members to select the plans that best meet their family healthcare needs and budget.
• Benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• A robust paid time-off program and paid holidays.