Staff SoC Design Engineer

Job Summary

The Waymo Compute Team is seeking a skilled engineer to define the architecture and microarchitecture for Waymo's next-generation autonomous vehicle SoCs. This role involves translating system-level requirements into detailed hardware specifications and RTL implementation, collaborating with various teams, and ensuring a timely and successful tapeout and product.

Responsibilities

• Define the architecture and microarchitecture for Waymo's next-generation autonomous vehicle SoCs
• Lead microarchitecture and implementation of IPs and subsystems, including high-performance cache/memory hierarchies, Network-on-Chip (NoC) interconnects, and custom accelerators
• Work with Architects, Firmware and Software teams to drive feature closure and develop microarchitecture specifications
• Perform power, area and performance exploration and optimization of digital designs
• Mentor other engineers and guide the technical side of relationships with external vendors

Requirements

• MS degree in Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience
• 10+ years of industry experience in ASIC/SoC digital design, microarchitecture, and integration, including ownership of major design blocks or subsystems
• Proven track record of technical leadership driving design and execution from concept to production, and hands-on experience with multiple successful ASIC tapeouts
• Strong understanding of computer architecture, memory systems, cache coherence, and high-speed on-chip interconnects
• Fluency in programming/scripting languages (e.g., Python, C++) for architectural modeling, design automation, and debug
• Strong debug and problem-solving skills, with the ability to root-cause complex issues across hardware and software boundaries

Preferred Qualifications

• PhD degree in Computer Engineering, Electrical Engineering, or a related field
• Experience in hardware/software co-design, including in mixed hardware/software datapaths, such as in the context of DSPs, GPUs, and ML accelerators
• Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies
• Knowledge of high performance and low power design techniques
• Fluency and comfort with AI tools to accelerate and improve design and debug
• Experience with Chisel (Scala) or other hardware DSLs for RTL generation