Jobs · Engineering · Oregon

Staff PDK Engineer

Analog Devices · Beaverton, OR · 3 wk ago
Engineering$135k–$202k/yrFull-time

About the role

As part of the PDK Development Group within the Engineering Enablement organization at ADI, you will be responsible for the ground up development of Process Design Kits (PDK) for ADI’s internal semiconductor process technologies used extensively in the design and manufacturing of analog, mixed signal and power management products in ADI. Experience working on Bipolar or High Voltage BCD processes is preferred. Be responsible for all aspects of PDK development for the assigned process/PDK and work with cross functional teams across PDK Development, Modeling, ESD and Process Engineering.

Responsibilities

  • Develop schematic symbols, CDFs, and callbacks.
  • Develop device layout generators (PCELLs).
  • Develop as well as improve physical verification (DRC/LVS) rule decks.
  • Develop rule decks for verifying Electrical Rule Checks (ERC).
  • Develop and validate Parasitic Extraction (PEX) technology files and flows.
  • Develop and improve automated QA procedures to improve the efficiency and integrity of the design kits.
  • Develop runsets for performing Layout vs Layout (LVL) and Schematic vs Schematic (SVS) checks.
  • Enhancing and maintaining netlist generation procedures for internal/external analog circuit simulation tools.
  • Work closely with the EDA software vendors to resolve tool bugs and drive new feature additions.
  • Work closely with the design teams to understand their requirements and collaborate with device modeling, process development, and foundry groups to enable the efficient use of CAD tools and methodologies.
  • Provide technical CAD support for ADI design community.

Requirements

  • BS/MS in Electrical or Computer Engineering with an emphasis on IC design and semiconductor processes.
  • Prior development experience and demonstrated understanding of CDFs, Callbacks, Layout P-cells, and schematic symbols.
  • Demonstrated experience in development of DRC, LVS and Parasitic Extraction runsets.
  • Proven skills in automation and programming languages (SKILL, Perl, Python, Tcl, Bash).
  • Understanding of analog/mixed signal simulation tools is preferred.
  • Thorough understanding of physical verification (DRC/LVS) tools and methodologies.
  • Knowledge of parasitic extraction tools from Siemens or Cadence.
  • Familiarity with revision control systems and collaboration tools.
  • Excellent verbal and written communication skills.
  • Excellent organizational and problem-solving skills.
  • Detail-oriented and versatile team player.

Preferred Education and Experience

  • Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or other related field of study with 8+ years of experience.
  • Master's degree in electrical engineering, Computer Engineering, Computer Science, or other related field of study with 6+ years of experience.

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