Staff Memory Design Engineer, HBM

Responsibilities

• Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size.
• Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts.
• Validate builds through reticle experiments, tape-out revisions, and simulation-to-silicon correlation, identifying required schematic edits.
• Prepare and maintain design documentation while contributing to best-known practices and departmental training.
• Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality.
• Manage layout and develop resources, track project tasks, and serve as the point of contact for design, layout, verification, and test issues.
• Prepare project status reports and lead design reviews to communicate progress and technical decisions.

Qualifications

• Coursework in CMOS Circuit Design, VLSI, and Analog Circuit Design, with understanding of device reliability and circuit floor planning.
• Proficiency with Cadence Virtuoso, and experience simulating with FINESIM, HSPICE, and VERILOG.
• Strong analytical and problem-solving skills with proven significant technical contributions and a record of innovation.
• Expertise in DRAM subsystem architecture, specification, operation, or design, including cross-department technical leadership experience.
• Ability to proactively collaborate across multiple engineering organizations to optimize manufacturing quality, cost, reliability, and time-to-market.