Staff Digital Design Engineer

About the Role

We are seeking a Senior Lead Digital Designer to lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE-T1S, 100BASE-T1, 1000BASE-T1, and multi-gig automotive SerDes technologies). The role involves driving digital micro-architecture, state machines, PCS functionality, safety mechanisms, and end-to-end digital design across the PHY.

Responsibilities

• Architecture & Technical Leadership
  • Define and own digital subsystem micro-architecture for Automotive Ethernet PHYs, including:
    • PCS pipelines and encoding/decoding logic
    • Scramblers/descramblers, CRC engines, alignment & framing
    • Packet processing, link monitoring, error handling
    • Interface logic (MII, RMII, RGMII, GMII, XGMII depending on product line)
    • Processor-based SoC design
  • Perform system-level partitioning between digital, analog/mixed-signal, and firmware components.
  • Lead feasibility studies, power/performance trade-offs, and digital architecture exploration.
• RTL Design & Implementation
  • Develop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic.
  • Drive digital front-end flows including:
    • Lint, CDC/RDC, reset architecture, synthesis guidance
    • Timing constraints and logic optimization
  • Work with DV to define coverage goals, corner cases, and feature verification plans.
• System-Level Ownership
  • Translate system requirements, IEEE 802.3 specifications, and architecture documents into robust digital designs.
  • Work with mixed-signal teams to define:
    • Control interfaces to analog front-end blocks
    • Calibration engines, register programming flows, and digital-analog interaction models
  • Contribute to bring-up sequences, compliance testing, and system validation.
• Automotive Quality & Functional Safety
  • Ensure compliance with Automotive Ethernet standards, ISO 26262, and AEC-Q100 expectations.
  • Define and implement:
    • Safety mechanisms (BIST, LBIST/MBIST, error detection schemes)
    • Diagnostic monitors, timeout recovery logic, watchdogs, and fault reporting
  • Participate in FMEDA, DFA, and functional safety analysis.

Requirements

• Masters in Electrical Engineering, Computer Engineering, or related discipline.
• 7+ years experience in digital design for PHY, SerDes, networking ASICs, or communication ICs.
• Strong expertise in:
  • Verilog/SystemVerilog RTL design
  • High-speed digital logic, state machines, control logic
  • IEEE 802.3 Ethernet PCS, link training, and system control flows
  • Synthesis, STA, CDC/RDC methodology
• Proven track record across multiple production tape-outs.

Preferred Qualifications

• Experience with Automotive Ethernet standards: 10BASE-T1S, 100BASE-T1, 1000BASE-T1, 10GBASE-T1.
• Familiarity with PHY firmware-driven initialization and configuration flows.
• Strong debugging skills with logic analyzers, protocol analyzers, and post-silicon validation.
• Background in safety-critical digital logic designs.