Staff Design Verification Engineer

About the role

The Staff Design Verification Engineer will be responsible for developing SystemVerilog/UVM testbenches for the Memory Controller within Arm System IP. This role involves working closely with performance modeling, validation, and implementation teams to ensure all functional requirements and PPA goals are met.

Responsibilities

• Develop SystemVerilog/UVM testbenches for unit level focusing on Memory Controller verification.
• Build and maintain detailed verification plans.
• Generate and run test cases on logic simulation models.
• Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the microarchitecture.
• Define and implement functional coverage.
• Promote and demonstrate the Arm Core Beliefs and Behaviors.

Requirements

• Bachelor’s or Master’s degree in Computer Science or Electrical/Computer Engineering
• 7+ years experience in microprocessor, SoC, memory controller and/or interconnect IP design and verification
• Proficiency in scripting languages such as Python or Perl
• Knowledge of assertion-based languages such as SystemVerilog Assertions
• Experience with CPU or compute subsystem memory micro-architecture

Nice to have

• Knowledge of DRAM specification (e.g., LPDDR4/5, DDR4/5, HBM)
• Knowledge of bus protocols (e.g., AMBA5 CHI, AMBA4 ACE or AXI)
• Processor system knowledge including basic understanding of SoC systems as well as operating system software

Benefits

Arm offers a range of benefits including:

• Health and Wellness
• Work and Life Success
• Financial Rewards
• Development and Support

Pay

$249,900-$338,100 per year

Schedule

Hybrid working is offered, allowing employees to split their time between the office and other locations.