Staff Design Engineer, HBM Architecture

Responsibilities

• Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic
• Develop high speed, low latency datapath circuits supporting multi channel HBM architectures and wide internal buses
• Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes
• Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms
• Collaborate with multi-functional teams to translate specifications into robust micro architectures
• Collaborate with PHY, DFT, verification, and layout teams to ensure accurate functionality, testability, and manufacturability
• Contribute to design reviews, documentation, and technical mentoring across HBM programs
• Contribute to the use of AI-enabled tools (e.g., Microsoft Copilot and other approved AI solutions) to improve productivity, streamline workflows, analyze information, and accelerate problem solving

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 7+ years of relevant industry experience, or a Master's degree with 5+ years of relevant industry experience
• 3 + years of experience in high speed digital datapath design (memory, SerDes, or SoC datapath)
• 3+ years of hands on experience with digital schematic build, RTL, or mixed signal datapath implementations

Qualifications

• Strong understanding of HBM/DRAM architectures, including read/write data flow, timing, and multi channel operation
• Working knowledge of layout and floorplanning considerations for high speed datapath
• Familiarity with advanced process node challenges related to signal integrity, skew control, and power optimization