SSG Design Engineering Intern (Fall 2026)

About the role

The Cadence Silicon Solutions Group (SSG) is seeking Design Engineering Interns to join our R&D teams in San Jose, CA. This is an opportunity to work alongside world-leading innovators in computational software, semiconductor design IP, and system verification hardware.

Responsibilities

• Work on Digital Design tasks, or Design Verification tasks related to the Janus NoC IP product.
• For Digital Design projects, implement RTL in System Verilog, simulate and debug RTL logic, and optimize timing, area, and power goals using EDA tools.
• For Design Verification Team projects, develop test plans, write functional tests (UVM) and verification monitors (SVA), debug failures, analyze coverage information, and script verification flows.
• Collaborate closely with the Design, Verification, and Physical Design teams.

Requirements

• Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar field.
• Deep understanding of Digital Design and/or Design Verification fundamentals.
• Excellent automation skills using tools like Tcl, Perl, and shell scripting.
• Strong oral and written communication skills.
• Exposure to design automation tools is a plus.

Qualifications

Internship will be based in San Jose location. Ideal candidates should be from local schools near the office.

Skills

• System Verilog
• Tcl
• Perl
• Shell scripting
• UVM
• SVA

Benefits

Annual salary range for California is $35/hr to $62/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Pay

$35/hr to $62/hr

Schedule

Full-time internship based in San Jose, CA.