Sr Staff Engineer, Program/Project Test Readiness Lead- C Rack

People Management & Team Leadership

Talent Development & Mentorship: Directly manage, coach, and mentor a specialized team of Test Hardware and Software Engineers, fostering technical proficiency in advanced diagnostic test development and automated frameworks.

Performance Management: Define clear test engineering metrics, KPIs, and deliverables; conduct objective performance evaluations and outline robust engineering career paths.

Resource Optimization: Plan and manage engineering bandwidth, test equipment budgets (CapEx), and lab infrastructure allocations across concurrent high-visibility NPI initiatives.

Early Engagement & Design for Testability (DFT)

DFT Strategy Ownership: Drive comprehensive DFT/DFx technical reviews during early schematic and board layout design stages to maximize structural and functional test access.

Silicon Partner Collaboration: Engage directly with tier-1 silicon architects (e.g., Nvidia, Broadcom, Marvell, Intel, AMD) to embed built-in self-test (BIST), high-speed JTAG boundary scan architectures, and advanced custom diagnostic hooks.

Test Plan Architecture: Formulate unified product test specifications (PTS) defining rigorous test coverage matrices, test point allocations, and optimization bounds before design freeze.

Advanced Test Characterization & Process Development

Multi-Level Test Execution: Oversee the specification, architecture, and deployment of In-Circuit Test (ICT), Functional Test (FCT), System-Level Test (SLT), and Environmental Stress Screening (ESS/Burn-in) solutions.

Yield Optimization & Data Analytics: Analyze production data sets to identify false failures, test instabilities, and gauge R&R shortfalls, systematically driving continuous optimization of test limits and fixture designs.

NPI Core Prototyping: Provide hands-on engineering guidance for initial test vehicle bring-up and debugs, test fixture qualification, diagnostic software stability checks, and strict version control for test binaries.

Knowledge/Skills/Competencies

Industry Context: Proven experience deploying complex test vectors for high-speed digital systems, enterprise servers, hyperscaler infrastructure, or working directly alongside tier-1 silicon providers (Nvidia, Broadcom, Marvell).

Technical Expertise: Expert level understanding of DFT methodologies, IEEE 1149.x Boundary Scan (JTAG), high-speed serial links (PCIe Gen 5/6, SerDes), instrumentation automation, programming frameworks (Python, C/C++, LabVIEW), and database/data mining systems for statistical process control (SPC).

Leadership Strategy: Outstanding project management maturity with a focus on metrics-driven problem solving (Six Sigma Black Belt preferred); ability to translate technical yield constraints to business risks for C-suite and customer reviews.

Physical Demands

Duties of this position are performed in a normal office environment.

Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.

Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.

Occasional travel may be required.