Sr. SoC Power & Performance Architect, AI Hardware

What To Expect

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla's machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD) and Tesla's humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance.

What You'll Do

• Lead the definition of power requirements for AI accelerator SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints
• Own and drive cross-functional teams to deliver on competitive power key performance indicators (KPIs) for one or more major SoC IPs such as the compute fabric, memory subsystem, or multimedia subsystem
• Propose and drive power and performance optimizations throughout the design process, from concept to mass productization
• Apply low-power design techniques including multi-VT, clock gating, power gating, and Dynamic Voltage-Frequency Scaling (DVFS/AVS)
• Drive power-performance trade-off analysis to inform engineering reviews and product roadmap decisions
• Develop and refine power and performance models for processors and system-software architectures
• Partner with cross-functional teams (architecture, RTL design, implementation, verification, and performance engineering) throughout the design flow
• Represent the status of SoC power to the executive leadership team

What You'll Bring

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience
• Experience with power management, low-power architecture, and power optimization techniques (multi-Vth/power/voltage-domain design, clock gating, power gating, DVFS, AVS)
• Knowledge of energy-efficient chip design fundamentals and related tradeoffs
• Understanding of processors (GPU a plus), system-software architectures, and their performance/power modeling techniques
• Familiarity with performance monitors and simulators used in modern processor architectures
• Experience across the full product-delivery cycle (definition, architecture, design and implementation, testing, and productization)
• Strong grasp of performance/power estimation and optimization methodology
• Minimum 5 years of industry experience related to power/performance estimation and optimization (senior-level candidates with 10+ years in power management or low-power design/methodology strongly preferred)

Benefits

• Competitive pay
• Medical plans
• Dental (including orthodontic coverage) and vision plans
• Company Paid (Health Savings Accounts) HSA Contribution
• Flexible Spending Accounts (FSA)
• 401(k) with employer match
• Employee Stock Purchase Plans
• Other financial benefits
• Basic Life, AD&D Short-term and long-term disability insurance
• Employee Assistance Program
• Sick and Vacation time
• Paid Holidays
• Commuter benefits
• Employee discounts and perks program

Expected Compensation

$160,000 - $312,000/annual salary + cash and stock awards + benefits