Sr. Principal System Reliability Engineer ( Fellow)
Sr. Principal System Reliability Engineer (Fellow)
Job Id: 554
# of Openings: 0
Location: San Jose , CA (On-site)
Required Skills
- Master’s or PhD in Electrical Engineering, Physics (Optics/Photonics), or a related field.
- 12+ years of experience in silicon reliability, RAS architecture, or high-speed system validation.
- Working knowledge of Silicon Photonics and its integration with high-speed protocols like CXL and PCIe.
- Proficiency in Python for automation/modeling and C/C++ for low-level hardware diagnostics.
- Proven ability to manage technical relationships with external partners and translate customer requirements into internal architectural specifications.
Preferred Qualifications
- Familiarity with 2.5D/3D packaging technologies (e.g., CoWoS, SoIC) and their associated reliability challenges.
- Exposure to silicon photonics, laser physics, or optical networking.
- Experience working with major foundries (e.g., TSMC) on advanced silicon integration.
Salary Range
$185,000 - $290,000
Strategic Partnerships & Qualification
Act as the primary technical lead in partnerships with HyperScaler engineering teams to define "Gold Standard" qualification strategies for optical I/O.
Viability Data Gathering
Architect and execute data-collection frameworks that capture long-term performance metrics, proving out the reliability of TeraPHY™ and SuperNova™ technologies under real-world cloud workloads.
Technology Readiness
Develop the documentation and statistical proof points required to transition Silicon Photonics from a cutting-edge innovation to a qualified, high-volume product ready for disaggregated compute environments.
Architectural Scope
Define hardware and firmware features for Reliability, Availability, and Serviceability (RAS), ensuring optical chiplets meet or exceed the standards of traditional copper-based silicon.
EIC/PIC Failure Modeling
Build predictive models (FIT) that integrate the unique failure modes of Photonic Integrated Circuits—such as laser frequency drift and ring resonator tuning—with standard Electronic Integrated Circuit aging.
Diagnostics Firmware
Develop C/C++ diagnostic kernels and real-time health-monitoring tools to identify and mitigate hardware anomalies before they impact system liveness.
Fault Simulation
Create automated environments to simulate transient optical noise and hardware-level faults within architectural models and post-silicon lab environments.
Benefits
Equal Opportunity Employer
Pay
$185,000 - $290,000
Schedule
On-site
Contact Information
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