Sr. Principal – Server Firmware & System Architecture

Key Responsibilities

• Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems
• Drive adoption of PCIe-based fabrics for disaggregated compute, memory, and accelerator scalability
• Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads
• Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem
• Drive innovation in server BIOS/UEFI architecture, OpenBMC-based platform management, Redfish APIs for scalable infrastructure control, and lifecycle provisioning frameworks
• Lead system bring-up and ensure seamless firmware-hardware-software integration across complex AI platforms
• Define the technical vision and multi-year firmware roadmap for AI infrastructure platforms
• Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads
• Drive memory performance optimization across DDR, NUMA, and emerging memory expansion technologies
• Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads
• Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers
• Influence industry standards across OpenBMC, Redfish, OCP, and related consortia
• Mentor senior engineers and grow deep technical bench strength across the organization
• Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation

Basic Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field
• 15+ years of experience in system architecture, server firmware, or platform engineering
• Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks
• Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6)
• Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms
• Strong programming experience in C/C++ and low-level system software
• Proven track record of leading cross-functional, large-scale architecture initiatives

Preferred Qualifications

• Master's degree or PhD in Computer Science, Electrical Engineering, or a related field
• Experience with rack-scale composable infrastructure and disaggregated architectures
• Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design
• Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs
• Experience with platform lifecycle management systems and fleet-level automation
• Contributions to industry standards bodies or open-source firmware ecosystems
• Demonstrated ability to define multi-year technical roadmaps and influence executive strategy