Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

About the role

Annapurna Labs, part of Amazon Utility Computing, designs custom silicon and software that accelerate cloud innovation. Our custom SoCs power Amazon Machine Learning servers, including AWS Inferentia and Trainium systems for inference and training. As an ASIC Physical Design Methodology Engineer on the Cloud-Scale Machine Learning Acceleration team, you will define and optimize physical design and verification methodologies (RTL2GDS) for ML accelerator chips in advanced process nodes, working at massive scale with rapid integration of emergent technologies.

Responsibilities

• Define, develop, and deploy innovative physical design and verification methodologies (RTL2GDS) for ML accelerator chips in advanced nodes
• Drive optimizations in CAD flows and methodologies for PPA and TAT improvements
• Work with EDA tool vendors to evaluate new methods, resolve bugs, and improve usability
• Fine-tune cloud infrastructure to improve compute and storage utilization for physical design work
• Interface directly with RTL, Physical Design, Package Design, and DFT teams to improve methodologies and efficiencies
• Independently troubleshoot digital tool flow usage and deploy solutions
• Build scalable, efficient flows using scripting languages (TCL, Python) to support parallel design developments
• Create dashboards and central reports for project tracking and visualizing QoR/stats

Requirements

• 7+ years of ASIC implementation, synthesis, STA, and physical design in deep sub-micron nodes (16nm or smaller)
• Bachelor's degree in Electrical Engineering or a related field
• Knowledge of implementing chips with multiple power islands and power gating
• Experience leading or solely developing methodology and scripts for physical synthesis
• Experience with low-power design techniques
• Experience leading technical initiatives and key deliverables
• Experience with version control systems and CI/CD pipeline implementation

Qualifications

• Master's degree or Ph.D. in Electrical Engineering or related field
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs

Benefits

• Health insurance (medical, dental, vision, prescription)
• Basic Life & AD&D insurance with option for Supplemental life plans
• Employee Assistance Program (EAP) and Mental Health Support
• Medical Advice Line
• Flexible Spending Accounts
• Adoption and Surrogacy Reimbursement coverage
• 401(k) matching
• Paid time off
• Parental leave

Pay

• Cupertino, CA: $213,000 – $287,500 annually
• Austin, TX: $185,200 – $250,000 annually

Compensation includes sign-on payments and restricted stock units (RSUs); final offer based on experience, qualifications, and location.

Company: Annapurna Labs (U.S.) Inc. • Job ID: A10583678