Sr. Hardware Engineer - ML Acceleration, Annapurna Labs

About the role

Annapurna Labs, a part of AWS Utility Computing, is seeking a Sr. Hardware Engineer to lead the design and validation of AWS's next-generation ML chips, cards, and server integrations. The ideal candidate will have expertise in PCIe and Serdes topics, and will contribute to the creation of customized platforms that meet AWS's high standards.

Responsibilities

• Design and optimize hardware for AWS data centers
• Provide leadership in applying new technologies to large-scale server deployments
• Deliver world-class customer experiences through continuous improvement
• Collaborate with cross-functional teams to develop innovative solutions
• Lead technical initiatives and key deliverables

Requirements

• 7+ years of ASIC implementation, synthesis, STA, and physical design in deep sub-micron nodes (16nm or smaller)
• 7+ years of digital design in communication systems
• 7+ years of full-custom analog or RF layout experience
• 7+ years of wireless communications systems and implementation experience
• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow
• 7+ years of verification in communication systems
• 5+ years of UVM, C, System C, and scripting experience
• 3+ years of emulation experience

Qualifications

• Bachelor's degree in Electrical Engineering or a related field
• Knowledge of UVM and Matlab
• Knowledge of implementing chips with multiple power islands and power gating
• Knowledge of multiple access systems including OFDMA, TDMA, and CDMA
• Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints
• Knowledge of serial protocols including SPI, I2C, I3C, and UART
• Knowledge of Python and Embedded C programming
• Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering
• Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
• Experience leading or solely developing methodology and scripts for physical synthesis
• Experience taping out chips that have gone into high volume production
• Experience developing products for volume production
• Experience in low power design techniques
• Experience delivering products to volume production
• Experience in modem L1/L2 algorithms development and architectures
• Experience in developing link and system level simulators using MATLAB, Python, or C++
• Experience in test setup automation using MATLAB, Python, or Pearl
• Experience with Agile, TDD, BDD, CI, and Git
• Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors
• Experience leading technical initiatives and key deliverables
• Experience with version control systems and CI/CD pipeline implementation
• Experience in Bare Metal Environment development, including linker scripts, page tables, and NVIC

Skills

• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring-up and post-silicon validation

Benefits

Base salary range: $183,000.00 - $247,600.00 USD annually

Includes sign-on payments and RSUs

Comprehensive benefits package including:

• Health insurance (medical, dental, vision, prescription, life, AD&D, EAP, mental health support, medical advice line, flexible spending accounts, adoption and surrogacy reimbursement)
• 401(k) matching
• Paid time off
• Parental leave

Learn more about our benefits at https://amazon.jobs/en/benefits