Sr Digital Design Engineer

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

About the Role

Micron is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. This role is responsible for RTL design, implementation, synthesis, timing analysis, power optimization, and design quality throughout the RTL-to-GDS flow. The engineer will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA (Power, Performance, Area) objectives for next-generation memory products.

Responsibilities

• Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets.
• Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities.
• Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality.
• Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios.
• Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market.

Requirements

• Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years of experience in digital ASIC/RTL design.
• Proven experience developing RTL for complex digital designs from specification through implementation handoff.
• Strong knowledge of ASIC front-end design flows including RTL design, functional verification, logic synthesis, CDC/RDC analysis, and static timing analysis (STA).
• Experience developing and maintaining design constraints (SDC), including clocks, timing exceptions, I/O constraints, and multi-mode multi-corner timing scenarios.
• Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
• Experience with low-power design methodologies, UPF-based power intent, timing constraints, and PPA optimization.

Preferred Qualifications

• Experience developing RTL for memory products or other high-performance digital designs.
• Familiarity with CMOS digital and mixed-signal circuit concepts.
• Experience collaborating across architecture, verification, and physical implementation teams to resolve integration and design challenges.
• Demonstrated ability to improve engineering productivity through process improvements, automation, and enhanced design methodologies.
• Strong communication, problem-solving, and teamwork skills, with the ability to demonstrate AI-assisted technologies and generative AI tools to improve engineering efficiency and collaboration.

Benefits

• A choice of medical, dental, and vision plans enabling team members to select the plans that best meet their family healthcare needs and budget.
• Benefit programs that help protect income if unable to work due to illness or injury, and paid family leave.
• Robust paid time-off program and paid holidays.