Sr. DFT Design Engineer, AWS Machine Learning Acceleration

About the role

Description Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies.

Responsibilities

• Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
• Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
• Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals
• Mentor and develop junior engineers through code reviews, methodology training, and technical guidance
• Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up

Requirements

• Bachelor's degree in computer science, electrical engineering, or related field
• 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience
• Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Experience with automation script development

Qualifications

• Bachelor's degree in computer science, electrical engineering, or related field
• Master's degree or Ph.D. degree in Electrical Engineering or related field preferred
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring-up and post-silicon validation
• Experience with gate-level testing and multi-clock design practices (CDC)
• Good breadth of knowledge in chip design from micro-architecture through physical design
• Good knowledge of design verification (DV) simulation methodologies
• Strong programming and scripting skills in Perl, Python or Tcl
• Experience with industry standard DFT/SCAN/ATPG tools
• Experience with STA constraints development and analysis for DFT modes

Skills

• Good breadth of knowledge in chip design from micro-architecture through physical design
• Good knowledge of design verification (DV) simulation methodologies
• Strong programming and scripting skills in Perl, Python or Tcl
• Experience with industry standard DFT/SCAN/ATPG tools
• Experience with STA constraints development and analysis for DFT modes

Benefits

• Comprehensive benefits including health insurance, medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage
• 401(k) matching
• Paid time off
• Parental leave

Pay

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location.

USA, TX, Austin - 159,200.00 - 215,300.00 USD annually

Company - Annapurna Labs (U.S.) Inc.
Job ID: A10409021