Sr Datacenter GPU Lead Power Constrained Performance Architect

About the role

AMD’s Datacenter Performance Group is seeking a senior Power & Performance Architect to drive the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role involves owning the Perf@Power attainment of a leading generation of our Instinct accelerators, providing cross-functional leadership for a virtual team that drives all aspects of Perf@Power attainment, including pre-Si modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, and methodology innovations and development. Passion for performance and power efficiency, influence without authority, and excellent communication skills are key ingredients for success in this role.

Responsibilities

• Own power-constrained performance modeling, projections, implementation target setting, and attainment tracking from Concept-exit (pre-si) to Product launch (post-si) for AMD Instinct AI/ML/HPC accelerators.
• Work with business unit and product architecture to define product configurations, capabilities, and Power & Performance (P&P) targets.
• Cross-functionally lead P&P attainment by collaborating with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, and Post-si validation.
• Roll-up Power/Performance readouts, present in executive forums, and motivate cross-functional teams on power efficiency improvements.
• Mentor junior engineers and develop skillsets and methodologies in the team for important PPA domains like Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade-offs and attainment, Silicon Power/Performance debug, Post-Si calibration of models, and Workload power analysis.

Requirements

• Background in Computer Architecture, Processor/Accelerator development.
• Experience in Power/Performance projections, modeling, and optimization at SoC or System level.
• Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc.).
• Familiarity with post-silicon power/performance debug and model correlation.
• Fluency in communicating with various engineering teams, business leads, and executive management.
• Knowledge of DL/ML/LLM/MoE workloads will be a bonus.

Qualifications

Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field.

This role is not eligible for visa sponsorship.

Benefits

AMD offers a comprehensive benefits package. For more details, see AMD benefits at a glance.