Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration - Annapurna Labs

About the role

As a member of the Utility Computing (UC) organization within AWS, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services. Annapurna Labs, our organization within AWS UC, designs silicon and software that accelerates innovation, enabling cloud solutions that solve previously unimaginable challenges.

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As part of the Cloud-Scale Machine Learning Acceleration team, you’ll design and optimize hardware in our data centers, including AWS Inferentia, our custom-designed machine learning inference datacenter server. Your work will ensure high design quality while making critical trade-offs in performance, power, and area.

Responsibilities

• Integrate multiple subsystems into a top-level SOC, ensuring correct clock, reset, functional, and DFT signal routing.
• Implement and deliver high-performance, area- and power-efficient RTL to meet design targets and specifications.
• Analyze design, microarchitecture, or architecture to make trade-offs based on features, power, performance, or area requirements.
• Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing-clean designs with constraints.
• Perform lint and clock domain crossing quality checks on the design.
• Collaborate with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing, and back-end teams.

Requirements

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of experience in RTL design for SOC.
• 5+ years of VLSI engineering experience.
• 5+ years of experience with code quality tools including Spyglass, LINT, or CDC.

Preferred Qualifications

• Master's degree or Ph.D. in Electrical Engineering or a related field.
• Experience scripting for automation (e.g., Python, Perl, Ruby).
• Strong analytical skills, attention to detail, and effective communication abilities.
• Experience with microarchitecture, SystemVerilog RTL, assertions, and SDC constraints.
• Familiarity with data path design, interconnects, and AXI protocol.

Skills

• Proficiency with assertions and debugging RTL test failures.
• Familiarity with scripting in Python.
• A "Learn and Be Curious" mindset.

About the team

Our team is dedicated to supporting new members with a broad mix of experience levels and tenures. We foster an environment that celebrates knowledge-sharing and mentorship, with senior members providing one-on-one guidance and thorough code reviews. We prioritize your career growth, assigning projects that develop your engineering expertise and empower you to tackle more complex tasks in the future.

Pay

• USA, CA, Cupertino: $183,000.00 - $247,600.00 USD annually.
• USA, TX, Austin: $159,200.00 - $215,300.00 USD annually.

Your Amazon package includes sign-on payments, restricted stock units (RSUs), and comprehensive benefits such as health insurance (medical, dental, vision, prescription), Basic Life & AD&D insurance, supplemental life plans, EAP, mental health support, flexible spending accounts, 401(k) matching, paid time off, parental leave, adoption and surrogacy reimbursement, and more. Learn more about our benefits.