SPE HARDWARE ARCHITECTURE

About the role

Rambus, a premier chip and silicon IP provider, is seeking an exceptional Memory Controller Architect and Technical Director to join our Silicon IP (SIP) team. You will work alongside some of the brightest inventors and engineers in the world to develop products that make data faster and safer. This full-time leadership position is an individual-contributor role reporting to the VP of Engineering.

You will architect highly reputed, high-performance, cutting-edge memory controllers for data centers and AI applications. This fast-growing market, driven by demand from tier-1 customers, offers ample opportunity for innovation and differentiation.

Responsibilities

• Architect next-generation memory controllers for data-center and AI workloads.
• Define micro-architecture, performance targets, power budgets, and area constraints.
• Collaborate with verification, implementation, and software teams to ensure successful product delivery.
• Engage with customers and internal stakeholders to gather requirements and drive technical roadmaps.
• Mentor junior engineers and contribute to patent filings and technical publications.

Requirements

• 10+ years of experience in memory-system or memory-controller architecture.
• Deep expertise in DDR, LPDDR, HBM, or emerging memory technologies.
• Strong background in performance modeling, power analysis, and RTL design.
• Familiarity with EDA flows (simulation, synthesis, timing closure).
• Excellent communication skills and ability to influence cross-functional teams.

Qualifications

• MS or PhD in Electrical/Computer Engineering or related field.
• Proven track record of shipping high-performance memory controllers.
• Experience with data-center or AI/ML workloads is a plus.