Software Engineering Intern - Design Automation (Spring 2027 Co-Op)

About the Role

Rivian internships are experiences optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2027 and 2029. Rivian's Internship Program requires active student enrollment. Information regarding your expected degree completion date is collected solely to verify eligibility and determine your availability for future full-time opportunities.

Our Spring Co-Op program runs from Jan - Aug, 2027. In order to be considered for this role, you must be available to work full time (40 hours per week), onsite, for the entire duration. If you are unable to work during the spring semester, please apply to our Summer Internship Program.

Responsibilities

• Develop Custom Automation Scripts: Write and deploy SKILL, Python, and TCL scripts within Cadence Allegro and OrCAD to eliminate manual data entry during schematic capture and board routing.
• Integrate ECAD/MCAD Workflows: Create automated bridges between Cadence tools and mechanical CAD software to ensure accurate, real-time synchronization of complex EV packaging constraints and board outlines.
• Enhance Component Library Management: Build tools to automatically generate, verify, and update PCB footprint and schematic symbol libraries by syncing directly with Rivian’s Product Lifecycle Management (PLM) database.
• Implement Advanced Rule Checking: Program custom Design Rule Checks (DRCs) tailored to Rivian's high-voltage and high-speed signal integrity requirements, preventing manufacturing errors before tape-out.
• Deploy and Document Toolchains: Package the developed automation tools into user-friendly interfaces, write technical documentation, and train the hardware engineering team to adopt the new workflows.

Qualifications

• Must be currently pursuing a bachelors or masters degree at an accredited university.
• Actively pursuing a degree or one closely related in computer science, electrical engineering, mechatronics, or similar.
• Possesses strong programming fundamentals with proficiency in Python, TCL, or C++, alongside an aptitude for learning proprietary EDA languages like Cadence SKILL.
• Demonstrates foundational knowledge of schematic capture and PCB layout processes, ideally with academic or project experience using Cadence OrCAD, Allegro, or similar ECAD platforms.
• Understands core hardware design principles, including component lifecycle management, basic signal integrity, and standard manufacturing constraints.
• Exhibits strong problem-solving skills with a track record of personal projects or coursework focused on software automation, API integration, or streamlining repetitive technical workflows.

Pay

The salary range for this role is $33.00-51.00/HR for Palo Alto based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.