SoC Physical Verification Engineer, HBM

About the role

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. As a Physical Verification Engineer in the Heterogeneous Integration Group (HIG), you will be a key technical contributor responsible for defining, executing, and driving sign‑off quality physical verification flows for next‑generation HBM logic die and memory‑centric SoCs. You will work across physical design, design rule development, EDA tool teams, foundry interfaces, and product engineering teams to deliver tape‑out‑ready silicon under aggressive schedule, quality, and reliability constraints.

Responsibilities

• Implement physical verification sign‑off for full‑chip and hierarchical designs, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), Physical Electrical Rule Check (PERC), antenna checking, and Design for Manufacturability (DFM).
• Implement and debug foundry‑qualified rule decks, manage waivers, and drive clean closure while ensuring compliance with advanced‑node foundry requirements.
• Perform reliability verification across multiple power domains, including electrostatic discharge (ESD), latch‑up, electromigration, floating nets, and connectivity checks.
• Run density, metal fill, and chemical mechanical polishing (CMP) checks to ensure yield‑aware manufacturability at 3 nm and below.
• Perform parasitic resistance‑capacitance (RC) extraction and support correlation of physical verification results with post‑silicon measurements.
• Develop, maintain, and optimize physical verification flows, automation, and regression infrastructure using Python, Tcl, Perl, or similar scripting languages.
• Drive adoption of machine learning (ML) and artificial intelligence (AI)‑based physical verification and power‑performance‑area (PPA) optimization tools.
• Partner with physical design, custom layout, CAD, RTL, product engineering, EDA, and foundry teams—including direct collaboration with TSMC—from design kick‑off through tape‑out readiness and sign‑off decision gates.
• Demonstrate AI to develop AI‑assisted development workflows.

Minimum Qualifications

• Experience with full‑chip or block‑level physical verification for advanced‑node system‑on‑chip, memory, or heterogeneous integration designs.
• Experience in physical verification methodologies, including DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign‑off.
• Experience using industry physical verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development or customization.
• Working knowledge of full RTL‑to‑GDS implementation flows, including place‑and‑route, extraction, and their impact on physical verification outcomes.
• Ability to drive verification closure by maintaining strong communication with multi‑functional teams in a global engineering environment.
• Proficiency with demonstrating AI and AI‑enabled development workflows.

Preferred Qualifications

• Experience with high‑bandwidth memory (HBM), DRAM, or memory‑centric system‑on‑chip physical verification, including multi‑die, chiplet, or 2.5D/3D integration.
• Background in GPU, CPU, or high‑performance accelerator physical implementation at advanced process nodes with aggressive sign‑off and tape‑out schedules.
• Familiarity with foundry develop rule documents, front‑end‑of‑line (FEOL) and back‑end‑of‑line (BEOL) rules, and advanced develop‑for‑manufacturability guidelines.
• Exposure to post‑silicon failure analysis, yield learning, or layout‑based debug with correlation between physical verification results and silicon behavior.
• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience, with 2+ years of relevant industry experience.

Pay

US base salary range: $97,000 – $205,000 per year. Additional compensation may include bonuses, equity, and benefits. Individual pay is determined by location, knowledge, skills, experience, tenure, and education.

Benefits

• Choice of medical, dental, and vision plans.
• Benefit programs that protect income if unable to work due to illness or injury.
• Paid family leave.
• Robust paid time‑off program and paid holidays.
• Additional programs designed to support wellbeing, peace of mind, and future planning.