SOC Physical Design Static Timing Analysis Engineer

About the Role

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.

Responsibilities

• Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
• Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
• Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
• Define methodologies to produce high-quality timing models and enable efficient physical design execution.
• Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans and binning strategies.
• Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
• Collaborate with architecture, clocking design, DFT, and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
• Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.

Requirements

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Bachelor's degree with 8+ years, or master’s degree with 6+ years, or PhD with 4+ years in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
• 3+ years of experience with the following skills:
  • Strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques.
  • Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.

Skills

• Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
• Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
• Knowledge of tools, flows, and methodologies for high-performance physical design.
• Strong communication skills and ability to articulate technical concepts effectively.
• DFT architecture knowledge is a strong plus.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $164,470.00 - $311,890.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.