SoC Logic Design Engineer

About the role

Join Intel's distinguished team as an SoC Logic Design Engineer. In this role, you will pioneer the development of cutting-edge System-on-Chip (SoC) solutions, contributing to Intel's mission of creating transformative technology that drives global innovation. As a key member of our team, you will have the opportunity to influence the architecture, design, and integration of next-generation SoCs. Your contributions will directly impact Intel's ability to deliver world-class products with optimal performance, power efficiency, and scalability, shaping the future of the semiconductor industry.

Key Responsibilities

• Develop high-quality logic designs, including Register Transfer Level (RTL) coding and simulations, for innovative SoCs.
• Collaborate with architects to define and implement microarchitecture features of SoC blocks.
• Integrate and validate Intellectual Property (IP) blocks and subsystems into full-chip SoC designs.
• Perform quality checks and optimize designs to meet power, performance, area, and timing objectives, ensuring seamless production readiness.
• Review verification plans to confirm design features are thoroughly verified and address any RTL test failures with corrective measures.
• Employ secure development practices to mitigate security risks and maintain design integrity.
• Work with IP providers to integrate and validate IPs at the SoC level.
• Drive quality assurance compliance to enable efficient IP-SoC handoffs.

Qualifications

• Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of relevant experience OR
  • Master's degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of relevant experience OR
  • PhD in Electrical Engineering, Computer Engineering, or a related field and 6+ months of experience.
• Experience:
  • Expertise in RTL development, System Verilog, and SoC logic integration.
  • Proficiency in microarchitecture definition, logic design, and simulation.
  • Strong understanding of SoC design methodologies, including timing/power convergence and physical implementation.
• PREFERRED QUALIFICATIONS:
  • Hands-on experience with Python, Perl, or other scripting languages.
  • Familiarity with advanced Front-End RTL Design tools such as Lint, CDC, Synthesis, and Static Timing Analysis (STA).
  • Experience in validation development, pre-silicon testing, and DFT/DFD tools.
  • Knowledge of industry-standard IPs, fabrics, and UVM-based verification.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 232,190.00 USD

Schedule

Shift 1 (United States of America)

Primary Location

US, Oregon, Hillsboro

Additional Locations

• US, California, Santa Clara
• US, Texas, Austin

Business Group

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).

Position of Trust

N/A

Work Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.