SoC Integration Engineer

About The Role

The Unified Intel Chassis (UIC) team develops scalable chassis architectures and Network-on-Chip technologies that power multiple SoCs inside Intel. We create high-performance, reusable IP components that enable product teams to deliver industry-leading performance while optimizing power and area efficiency. We are seeking an experienced SoC Integration Engineer to join our world-class team to work on cutting-edge technology that impacts millions of devices globally.

What You’ll Do

• Partner with SoC architecture teams to define and refine system-level chassis and interconnect requirements
• Design and integrate high-performance NoC / interconnect fabrics meeting power, performance, and area (PPA) targets
• Drive integration of IP blocks into SoC platforms, ensuring scalability and performance across products
• Collaborate with fabric IP development teams to enhance or customize reusable components
• Analyze trade-offs across performance, power, and area to influence architectural decisions
• Work closely with physical design teams to address floor planning and implementation constraints
• Support debug, validation, and bring-up activities for integrated SoC platforms
• Collaborate across global, cross-functional teams to deliver complex silicon solutions

Behavioral Traits That We Are Looking For

• Systems Thinking: Ability to understand and optimize complex SoC ecosystems end-to-end
• Ownership & Accountability: Drives deliverables independently while owning outcomes
• Collaboration & Influence: Builds strong partnerships across architecture, design, and global teams across multiple time zones
• Technical Leadership: Mentors junior engineers and contributes to technical direction
• Problem Solving: Proactively identifies risks and develops scalable solutions
• Adaptability: Thrives in a fast-paced, evolving technology environment
• Clear Communication: Effectively communicates complex technical concepts across audiences

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 6+ years of experience.
• Or a Master's degree in the same field with 4+ years of experience.
• You experience listed above must be in the following:
• SOC and/or IP design
• Experience in microarchitecture and design of IP systems, including 2+ years' experience in fabric design/integration
• Expertise in Verilog/System Verilog Design, Lint/CDC/RDC and timing constraints
• AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL
• Experience in analyzing power, performance and area trade-offs in designs
• Physical design to understand floorplan limitations

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